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| author | Jon Loeliger <jdl@freescale.com> | 2006-06-27 11:08:17 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2006-06-27 11:08:17 -0500 |
| commit | 894b773c8678ce68b01c99b02ffad236e470458b (patch) | |
| tree | b2354e1daf943e7ab1ae4befcccbb9712281cfd5 /include/configs | |
| parent | 321bbd41f9f8bc58ac76017b7d5dffb67382a99f (diff) | |
| parent | bc09cf3c2bfb8d54c659cbb332f79d0950982fd0 (diff) | |
| download | u-boot-imx-894b773c8678ce68b01c99b02ffad236e470458b.zip u-boot-imx-894b773c8678ce68b01c99b02ffad236e470458b.tar.gz u-boot-imx-894b773c8678ce68b01c99b02ffad236e470458b.tar.bz2 | |
Merge branch 'mpc86xx'
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8641HPCN.h | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 2a197be..b089769 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,7 +46,8 @@ #define CFG_RESET_ADDRESS 0xfff00100 -#undef CONFIG_PCI +/*#undef CONFIG_PCI*/ +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -209,8 +210,10 @@ #undef CFG_RAMBOOT #endif -#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#if defined(CFG_RAMBOOT) +#undef CFG_FLASH_CFI_DRIVER +#undef CONFIG_SPD_EEPROM +#define CFG_SDRAM_SIZE 256 #endif #undef CONFIG_CLOCKS_IN_MHZ @@ -295,7 +298,13 @@ #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + /* For RTL8139 */ +#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000 #define CFG_PCI2_MEM_BASE 0xa0000000 @@ -429,10 +438,10 @@ * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U #define CFG_DBAT7L 0x00000000 |