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authorWolfgang Denk <wd@pollux.denx.de>2006-03-12 21:33:52 +0100
committerWolfgang Denk <wd@pollux.denx.de>2006-03-12 21:33:52 +0100
commit795bee849603c7c2994ba20fcd96f3f9835ffd96 (patch)
tree905ce7474dcf0adfbab149df429bfdaef5d5e258 /include/configs
parent7b230f61db319d87d51449d4620d520822813fbb (diff)
parent2688e2f972bd124be87cb86bce58aa1b186b5aa7 (diff)
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Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc83xx
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/MPC8349ADS.h67
-rw-r--r--include/configs/TQM834x.h47
2 files changed, 112 insertions, 2 deletions
diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h
index d6d2fab..ef2e532 100644
--- a/include/configs/MPC8349ADS.h
+++ b/include/configs/MPC8349ADS.h
@@ -150,7 +150,7 @@
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
@@ -506,6 +506,10 @@
HRCWH_TSEC2M_IN_GMII )
#endif
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
@@ -515,7 +519,66 @@
HID0_ENABLE_M_BIT |\
HID0_ENABLE_ADDRESS_BROADCAST ) */
-#define CFG_HID2 0x000000000
+#define CFG_HID2 HID2_HBE
+
+/* DDR 0 - 256MB */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* 2G - 3G PCI */
+#ifdef CONFIG_PCI
+#define CFG_IBAT2L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT2L (0)
+#define CFG_IBAT2U (0)
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT4L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+#define CFG_IBAT5L (0)
+#define CFG_IBAT5U (0)
+#endif
+
+/* IMMRBAR */
+#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM, BCSR & FLASH */
+#define CFG_IBAT7L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
/*
* Internal Definitions
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 41f44c5..cec7e3e 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -417,11 +417,58 @@ extern int tqm834x_num_flash_banks;
HRCWH_TSEC2M_IN_GMII )
#endif
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
/* i-cache and d-cache disabled */
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 0x000000000
+/* DDR 0 - 512M */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 512M (no backing mem) */
+#define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI */
+#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+
+/* IMMRBAR */
+#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+/* FLASH */
+#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
/*
* Internal Definitions
*