Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

6 files changed, 18 insertions, 26 deletions

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index f3eee23..5a99d5f 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -99,7 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index ff24fa5..b31c2bb 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -97,7 +97,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 6295590..7a7e5a1 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -100,7 +100,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 9e16bb4..8bdec65 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -92,7 +92,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 9f01f9a..9a66ca8 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -99,6 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
@@ -114,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
+#define CONFIG_SYS_DDR_MODE_1		0x00440462
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400000
 
 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index cd98894..5a83296 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS	(CONFIG_SYS_FLASH_BASE \
 					 | CONFIG_SYS_PHYS_ADDR_HIGH)
 
-
 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 
-/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
-#define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
-					 ((x & 0x300000000ULL) >> 19)))
-#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
-#endif
-
 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 				 | 0x00001001)	/* port size 16bit */
 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/