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authorJerry Huang <Chang-Ming.Huang@freescale.com>2011-11-07 13:20:21 +0800
committerKim Phillips <kim.phillips@freescale.com>2011-11-07 18:34:40 -0600
commit6be55ee2252c364b16d99537bf9fe7d96d5c77b4 (patch)
tree1b06f01a606df48b5634aa2ed75efb9dc55d1e2f /include/configs
parentd37be07ee57e4390eb4e5529f9a481e334dbbe07 (diff)
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powerpc/mpc83xx: Add 33.33MHz support for mpc8360emds
The new MPC8360EMDS board changes the oscillator to 33.33MHz in order to support QE 500MHz since 2008. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/MPC8360EMDS.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 5a1e6f5..9604fda 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -39,6 +39,18 @@
/*
* System Clock Setup
*/
+#ifdef CONFIG_CLKIN_33MHZ
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK 33330000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN 33330000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ 33330000
+#endif
+
+#elif defined(CONFIG_CLKIN_66MHZ)
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
#else
@@ -48,10 +60,24 @@
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 66000000
#endif
+#else
+#error Unknown oscillator frequency.
+#endif
/*
* Hardware Reset Configuration Word
*/
+#ifdef CONFIG_CLKIN_33MHZ
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_8X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CE_PLL_VCO_DIV_4 |\
+ HRCWL_CE_PLL_DIV_1X1 |\
+ HRCWL_CE_TO_PLL_1X15 |\
+ HRCWL_CORE_TO_CSB_2X1)
+#elif defined(CONFIG_CLKIN_66MHZ)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
@@ -61,6 +87,7 @@
HRCWL_CE_PLL_DIV_1X1 |\
HRCWL_CE_TO_PLL_1X6 |\
HRCWL_CORE_TO_CSB_2X1)
+#endif
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\