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authorWolfgang Denk <wd@denx.de>2008-04-08 00:05:42 +0200
committerWolfgang Denk <wd@denx.de>2008-04-08 00:05:42 +0200
commit62479b181460f5bf99517b68059d5ba87908edd3 (patch)
treea68933d5d6b6ab8d06c107c421d6abb5d1669e74 /include/configs
parent5c395393cc9b85b14c5481dbcab6b67b54f31622 (diff)
parent066bebd6353e33af3adefc3404560871699e9961 (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-arm
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/davinci_dvevm.h44
-rw-r--r--include/configs/davinci_schmoogie.h19
-rw-r--r--include/configs/davinci_sonata.h18
-rw-r--r--include/configs/imx31_litekit.h167
-rw-r--r--include/configs/imx31_phycore.h190
-rw-r--r--include/configs/mx31ads.h170
-rw-r--r--include/configs/pmdra.h186
7 files changed, 785 insertions, 9 deletions
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 8ecd059..17d3b03 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -52,6 +52,9 @@
#define DV_EVM
#define CFG_NAND_SMALLPAGE
#define CFG_USE_NOR
+#define CFG_USE_INTEL_NOR /* Define this when your DVEVM has Intel
+ * flash instead of AMD flash
+ */
/*===================*/
/* SoC Configuration */
/*===================*/
@@ -60,6 +63,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
@@ -114,7 +135,7 @@
#ifdef CFG_USE_NAND
#undef CFG_ENV_IS_IN_FLASH
#define CFG_NO_FLASH
-#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#ifdef CFG_NAND_SMALLPAGE
#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CFG_ENV_SIZE SZ_16K
@@ -139,24 +160,31 @@
#undef CONFIG_SKIP_RELOCATE_UBOOT
#endif
#define CFG_ENV_IS_IN_FLASH
-#undef CFG_NO_FLASH
+#undef CFG_NO_FLASH
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
-#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#ifdef CFG_USE_INTEL_NOR
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+#else
+#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
+#endif
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
+#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 96c9a30..cb69535 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -35,6 +35,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x0432229c /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 2 /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178622 /* 4 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*=============*/
/* Memory Info */
/*=============*/
@@ -46,7 +64,6 @@
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index de8c4fa..b2c0d7d 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -60,6 +60,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
new file mode 100644
index 0000000..a6ed77a
--- /dev/null
+++ b/include/configs/imx31_litekit.h
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs), v3, tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; " \
+ "protect off all; erase 0xa00d0000 0xa01effff; " \
+ "cp.b 0x80000000 0xa00d0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xb4020000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_ENV_ADDR 0xa01f0000
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (64 * 1024)
+#define CFG_ENV_SIZE (64 * 1024)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
new file mode 100644
index 0000000..647b05b
--- /dev/null
+++ b/include/configs/imx31_phycore.h
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CFG_I2C_MX31_PORT2 1
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 0xfe
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#define CONFIG_BOOTDELAY 3
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootargs_flash=setenv bootargs $(bootargs) " \
+ "root=/dev/mtdblock2 rootfstype=jffs2\0" \
+ "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 $(uimage); bootm\0" \
+ "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; " \
+ "bootm 0x80000000\0" \
+ "unlock=yes\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "prg_uboot=tftpboot 0x80000000 $(uboot); " \
+ "protect off 0xa0000000 +0x20000; " \
+ "erase 0xa0000000 +0x20000; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
+ "prg_kernel=tftpboot 0x80000000 $(uimage); " \
+ "erase 0xa0040000 +0x180000; " \
+ "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
+ "prg_jffs2=tftpboot 0x80000000 $(jffs2); " \
+ "erase 0xa01c0000 0xa1ffffff; " \
+ "cp.b 0x80000000 0xa01c0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "uboot> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#define CFG_LOAD_ADDR 0 /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE 0xa0000000
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0x00 /* environment starts here */
+#define CFG_ENV_SIZE 4096
+#define CFG_I2C_EEPROM_ADDR 0x52
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
new file mode 100644
index 0000000..be7f3c6
--- /dev/null
+++ b/include/configs/mx31ads.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
+#define CONFIG_MX31_CLK32 32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Disabled for now due to build problems under Debian and
+ * a significant increase in the final file size: 144260 vs. 109536 Bytes
+ */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART 1
+#define CFG_MX31_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.23.168
+#define CONFIG_SERVERIP 192.168.23.2
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
+ "prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; " \
+ "protect off 0xa0000000 0xa001ffff; " \
+ "erase 0xa0000000 0xa001ffff; " \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0"
+
+#define CONFIG_DRIVER_CS8900 1
+#define CS8900_BASE 0xb4020300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0 /* memtest works on */
+#define CFG_MEMTEST_END 0x10000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR CSD0_BASE /* default load address */
+
+#define CFG_HZ 32000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE CS0_BASE
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128KiB */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SECT_SIZE (32 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+/* S29WS256N NOR flash has 4 32KiB small sectors at beginning and end.
+ * The rest of 32MiB is in 128KiB big sectors.
+ * U-Boot occupies the low 4 sectors,
+ * if we put environment next to it, we will have to occupy 128KiB for it.
+ * Putting it at the top of flash we use only 32KiB. */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 32 * 1024 * 1024 - CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#if 0 /* Doesn't work yet, work in progress */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes(~10x faster)*/
+#endif
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pmdra.h b/include/configs/pmdra.h
new file mode 100644
index 0000000..e170ee9
--- /dev/null
+++ b/include/configs/pmdra.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2008 Prodrive BV <pieter.voorthijsen@prodrive.nl>
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define CFG_PMDRA
+#define CFG_NAND_LARGEPAGE
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SYS_CLK_FREQ ((CFG_HZ_CLOCK * (CFG_DAVINCI_PLL1_PLLM + 1))/2)
+#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
+#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x10000000
+#define CFG_DAVINCI_ACFG2 0x00460385 /* NOR CE Config */
+#define CFG_DAVINCI_ACFG3 0x0822218c /* NAND CE Config */
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#define CFG_DAVINCI_NANDCE 3 /* Use CE3 for NAND */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178832 /* 8 banks , CAS = 4*/
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x12
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS 6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
+#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
+#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
+#define CFG_NS16550_COM2 0x01c20800 /* Base address of UART2 */
+#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED 50000 /* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CFG_USE_NAND
+#define CFG_NAND_BASE 0x04000000
+#undef CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)*/
+#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
+#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
+#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
+#define CFG_FLASH_PROTECTION 1
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_ENV_OVERWRITE
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS \
+ "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND "run nand"
+#define CONFIG_EXTRA_ENV_SETTINGS "ethaddr=00:11:22:33:44:55\n"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+/*=======================*/
+/* KGDB support (if any) */
+/*=======================*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */