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authorWolfgang Denk <wd@denx.de>2009-12-01 12:10:51 +0100
committerWolfgang Denk <wd@denx.de>2009-12-01 12:10:51 +0100
commit57bf140ac66f95c9c36c494e4d027551b5477b01 (patch)
tree78cc2602ee9dca3284e47f38d29380171fb53646 /include/configs
parent34ddbd171ba154e9afd83f07a07ad8b57ac592e3 (diff)
parent71636fa7c3de63de29c0f514d5c725eccb011657 (diff)
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Merge branch 'next-sync' of git://git.denx.de/u-boot-arm into next
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/VCMA9.h7
-rw-r--r--include/configs/a320evb.h222
-rw-r--r--include/configs/da830evm.h243
-rw-r--r--include/configs/devkit8000.h3
-rw-r--r--include/configs/imx27lite.h1
-rw-r--r--include/configs/omap3_beagle.h3
-rw-r--r--include/configs/omap3_evm.h3
-rw-r--r--include/configs/omap3_overo.h3
-rw-r--r--include/configs/omap3_pandora.h3
-rw-r--r--include/configs/omap3_sdp3430.h3
-rw-r--r--include/configs/omap3_zoom1.h3
-rw-r--r--include/configs/omap3_zoom2.h3
-rw-r--r--include/configs/sbc2410x.h7
-rw-r--r--include/configs/smdk2400.h7
-rw-r--r--include/configs/smdk2410.h7
-rw-r--r--include/configs/smdk6400.h2
-rw-r--r--include/configs/trab.h9
17 files changed, 511 insertions, 18 deletions
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 618b7f0..ebc81c4 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -33,9 +33,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h
new file mode 100644
index 0000000..fcc5563
--- /dev/null
+++ b/include/configs/a320evb.h
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Configuation settings for the Faraday A320 board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/a320.h>
+
+/*-----------------------------------------------------------------------
+ * CPU and Board Configuration Options
+ */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*-----------------------------------------------------------------------
+ * Timer
+ */
+#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*-----------------------------------------------------------------------
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 0x98200000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK 18432000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*-----------------------------------------------------------------------
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*-----------------------------------------------------------------------
+ * SDRAM controller configuration
+ */
+#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
+ FTSDMC020_TP0_TRP(1) | \
+ FTSDMC020_TP0_TRCD(1) | \
+ FTSDMC020_TP0_TRF(3) | \
+ FTSDMC020_TP0_TWR(1) | \
+ FTSDMC020_TP0_TCL(2))
+
+#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
+ FTSDMC020_TP1_INI_REFT(8) | \
+ FTSDMC020_TP1_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
+ FTSDMC020_BANK_DDW_X16 | \
+ FTSDMC020_BANK_DSZ_256M | \
+ FTSDMC020_BANK_MBW_32 | \
+ FTSDMC020_BANK_SIZE_64M)
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x12000000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x13F00000
+
+/*-----------------------------------------------------------------------
+ * Static memory controller configuration
+ */
+
+#include <asm/arch/ftsmc020.h>
+
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_1M | \
+ FTSMC020_BANK_MBW_8)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* support JEDEC */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+#define PHYS_FLASH_1 0x00000000
+#define PHYS_FLASH_2 0x00400000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x00060000
+#define CONFIG_ENV_SIZE 0x20000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
new file mode 100644
index 0000000..38e2ce1
--- /dev/null
+++ b/include/configs/da830evm.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA830_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+
+/*
+ * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
+#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
+#define CONFIG_SYS_FLASH_SPL_ACCESS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE 4096
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+
+/*
+ * U-Boot general configuration
+ */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "DA830-evm > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_EEPROM
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ENV
+#endif
+
+#ifdef CONFIG_USB_DA8XX
+#define CONFIG_CMD_USB /* include support for usb */
+#define CONFIG_CMD_STORAGE /* include support for usb */
+#define CONFIG_CMD_FAT /* include support for FAT/storage*/
+#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index bd5037e..1011770 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -66,6 +66,9 @@
/* Hardware drivers */
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* DM9000 */
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h
index 8ebb0bb..e219ccc 100644
--- a/include/configs/imx27lite.h
+++ b/include/configs/imx27lite.h
@@ -156,6 +156,7 @@
#define CONFIG_SYS_NAND_BASE 0xd8000000
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*
* SD/MMC
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 19a5ec9..024b9b8 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -97,6 +97,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index a5514ae..6709edc 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -101,6 +101,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index ffb515d..0f812a7 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -89,6 +89,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 6f21af3..0cafeb8 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -92,6 +92,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 229dc5e..d91c8ff 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -137,6 +137,9 @@
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/* DDR - I use Infineon DDR */
+#define CONFIG_OMAP3_INFINEON_DDR 1
+
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index da4b677..2aef973 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -98,6 +98,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 32cd6fd..5b03fb6 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -98,6 +98,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index e6886cf..025ad09 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -43,9 +43,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index a1beb65..fd51219 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -34,9 +34,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T core */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
-#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
+#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index c57751b..f9d1e55 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -33,9 +33,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index f6e1221..f644cd2 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -49,8 +49,6 @@
#define CONFIG_ENABLE_MMU
#endif
-#define CONFIG_MEMORY_UPPER_CODE
-
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 97f30ce..9827195 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -40,10 +40,11 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
-#define CONFIG_TRAB 1 /* on a TRAB Board */
-#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
+#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
+#define CONFIG_TRAB 1 /* on a TRAB Board */
+#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
/* automatic software updates (see board/trab/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1