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authorTom Rini <trini@ti.com>2014-06-05 17:38:30 -0400
committerTom Rini <trini@ti.com>2014-06-05 17:38:30 -0400
commit3e1fa221f94b7ae3389d166882b77f1da5895f22 (patch)
tree6edd72d4ea079605c4624999424b3577dbeb4d8b /include/configs
parent31e997f9212be04e7bbe9c05785d72c4931dcfd4 (diff)
parent353527d527b78297571c05b8a1687c92d42f6d20 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/T1040QDS.h6
-rw-r--r--include/configs/T104xRDB.h6
-rw-r--r--include/configs/T208xQDS.h5
3 files changed, 15 insertions, 2 deletions
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 2215ac8..f2a75ae 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -201,6 +201,12 @@ unsigned long get_board_ddr_clk(void);
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
+
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index e564cb7..8d6c51b 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -230,6 +230,12 @@
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
+
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 8dd2e49..59d142e 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -227,8 +227,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE