Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xx

6 files changed, 1616 insertions, 318 deletions

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
new file mode 100644
index 0000000..cecb225
--- /dev/null
+++ b/include/configs/MPC832XEMDS.h
@@ -0,0 +1,631 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+#define CONFIG_QE		1	/* Has QE */
+#define CONFIG_MPC83XX		1	/* MPC83xx family */
+#define CONFIG_MPC832X		1	/* MPC832x CPU specific */
+#define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66000000	/* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2X1 |\
+	HRCWL_CE_PLL_VCO_DIV_2 |\
+	HRCWL_CE_PLL_DIV_1X1 |\
+	HRCWL_CE_TO_PLL_1X3)
+
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+#endif
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRL		0x00000000
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE		128	/* MB */
+#define CFG_DDR_CS0_CONFIG	0x80840102
+#define CFG_DDR_TIMING_0	0x00220802
+#define CFG_DDR_TIMING_1	0x3935d322
+#define CFG_DDR_TIMING_2	0x0f9048ca
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_CLK_CNTL	0x02000000
+#define CFG_DDR_MODE		0x44400232
+#define CFG_DDR_MODE2		0x8000c000
+#define CFG_DDR_INTERVAL	0x03200064
+#define CFG_DDR_CS0_BNDS	0x00000007
+#define CFG_DDR_SDRAM_CFG	0x43080000
+#define CFG_DDR_SDRAM_CFG2	0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST		/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00000000	/* memtest region */
+#define CFG_MEMTEST_END		0x00100000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CFG_LBC_LBCR		0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* FLASH base address */
+#define CFG_FLASH_SIZE		16	/* FLASH size is 16M */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
+
+#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
+			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
+			BR_V)			/* valid */
+#define CFG_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CFG_BCSR		0xF8000000
+#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR	/* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* Access window size 32K */
+
+#define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801)	/* Port size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM		0xFFFFE9f7	/* length 32K */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#undef CFG_LB_SDRAM		/* The board has not SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
+#define CFG_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
+
+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM	0xfc006901
+
+#define CFG_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON	0x0063b723
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+
+#endif
+
+/*
+ * Windows to access PIB via local bus
+ */
+#define CFG_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
+#define CFG_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
+
+/*
+ * CS2 on Local Bus, to PIB
+ */
+#define CFG_BR2_PRELIM	0xf8008801	/* CS2 base address at 0xf8008000 */
+#define CFG_OR2_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+
+/*
+ * CS3 on Local Bus, to PIB
+ */
+#define CFG_BR3_PRELIM	0xf8010801	/* CS3 base address at 0xf8010000 */
+#define CFG_OR3_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8323@0"
+#define OF_SOC			"soc8323@e0000000"
+#define OF_QE			"qe@e0100000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8323@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE	0x7F
+#define CFG_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET	0x3000
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_MMIO_BASE	0x90000000
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_PHYS		0xE0300000
+#define CFG_PCI_IO_SIZE		0x100000	/* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS	0x00000000
+#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+
+
+#ifdef CONFIG_PCI
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"Freescale GETH"
+
+#define CONFIG_UEC_ETH1		/* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM	2	/* UCC3 */
+#define CFG_UEC1_RX_CLK		QE_CLK9
+#define CFG_UEC1_TX_CLK		QE_CLK10
+#define CFG_UEC1_ETH_TYPE	FAST_ETH
+#define CFG_UEC1_PHY_ADDR	3
+#define CFG_UEC1_INTERFACE_MODE	ENET_100_MII
+#endif
+
+#define CONFIG_UEC_ETH2		/* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM	3	/* UCC4 */
+#define CFG_UEC2_RX_CLK		QE_CLK7
+#define CFG_UEC2_TX_CLK		QE_CLK8
+#define CFG_UEC2_ETH_TYPE	FAST_ETH
+#define CFG_UEC2_PHY_ADDR	4
+#define CFG_UEC2_INTERFACE_MODE	ENET_100_MII
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_PCI \
+				| CFG_CMD_I2C) \
+				& \
+				~(CFG_CMD_ENV \
+				| CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C) \
+				& \
+				~(CFG_CMD_ENV \
+				| CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C  )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_LOAD_ADDR		0x2000000	/* default load address */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2		HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+
+/* BCSR: cache-inhibit and guarded */
+#define CFG_IBAT2L	(CFG_BCSR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U	CFG_IBAT3U
+
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#else
+#define CFG_IBAT6L	(0)
+#define CFG_IBAT6U	(0)
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_ETHADDR	00:04:9f:ef:03:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
+#endif
+
+#define CONFIG_BAUDRATE	115200
+
+#define CONFIG_LOADADDR	200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=1000000\0"						\
+   "ramdiskfile=ramfs.83xx\0"						\
+   "fdtaddr=400000\0"							\
+   "fdtfile=mpc832xemds.dtb\0"						\
+   ""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 5bed2d0..0460be9 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -60,17 +60,6 @@
 #endif
 #endif
 
-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
 #define CFG_IMMR		0xE0000000
@@ -82,7 +71,7 @@
 /*
  * DDR Setup
  */
-#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_ECC			/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 
@@ -101,8 +90,15 @@
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_BASE
 #define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING
 
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CFG_DDRCDR_VALUE	0x80080001
+
 #if defined(CONFIG_SPD_EEPROM)
 /*
  * Determine DDR configuration from I2C interface.
@@ -113,6 +109,21 @@
  * Manually set up DDR parameters
  */
 #define CFG_DDR_SIZE		256		/* MB */
+#if defined(CONFIG_DDR_II)
+#define CFG_DDRCDR		0x80080001
+#define CFG_DDR_CS2_BNDS	0x0000000f
+#define CFG_DDR_CS2_CONFIG	0x80330102
+#define CFG_DDR_TIMING_0	0x00220802
+#define CFG_DDR_TIMING_1	0x38357322
+#define CFG_DDR_TIMING_2	0x2f9048c8
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_CLK_CNTL	0x02000000
+#define CFG_DDR_MODE		0x47d00432
+#define CFG_DDR_MODE2		0x8000c000
+#define CFG_DDR_INTERVAL	0x03cf0080
+#define CFG_DDR_SDRAM_CFG	0x43000000
+#define CFG_DDR_SDRAM_CFG2	0x00401000
+#else
 #define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CFG_DDR_TIMING_1	0x36332321
 #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
@@ -127,6 +138,7 @@
 #define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
+#endif
 
 /*
  * SDRAM on the Local Bus
@@ -140,19 +152,20 @@
 #define CFG_FLASH_CFI				/* use the Common Flash Interface */
 #define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* flash size in MB */
+#define CFG_FLASH_SIZE		32		/* max flash size in MB */
 /* #define CFG_FLASH_USE_BUFFER_WRITE */
 
 #define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
-				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
 				BR_V)			/* valid */
-
-#define CFG_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
+#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
 
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
 
 #undef CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
@@ -197,7 +210,11 @@
 #define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CFG_LBC_LBCR	0x00000000
 
-#define CFG_LB_SDRAM	/* if board has SRDAM on local bus */
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
+ */
+#undef CFG_LB_SDRAM
 
 #ifdef CFG_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
@@ -314,6 +331,7 @@
 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
 #ifdef  CFG_HUSH_PARSER
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index cbdbb29..37bbfb3 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -21,7 +21,7 @@
  */
 
 /*
- MPC8349E-mITX board configuration file
+ MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
 
  Memory map:
 
@@ -31,11 +31,11 @@
  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
- 0xF000_0000-0xF000_FFFF Compact Flash
+ 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  0xF001_0000-0xF001_FFFF Local bus expansion slot
- 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385
- 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB)
- 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB)
+ 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
+ 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
+ 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
 
  I2C address list:
 						Align.	Board
@@ -56,7 +56,9 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#undef DEBUG
+#if (TEXT_BASE == 0xFE000000)
+#define CFG_LOWBOOT
+#endif
 
 /*
  * High Level Configuration Options
@@ -64,14 +66,26 @@
 #define CONFIG_MPC834X		/* MPC834x family (8343, 8347, 8349) */
 #define CONFIG_MPC8349		/* MPC8349 specific */
 
-#define CONFIG_PCI
+#define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
+
+
+/* On-board devices */
 
+#ifdef CONFIG_MPC8349ITX
 #define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
-#define CONFIG_RTC_DS1337
+#define CONFIG_VSC7385		/* The Vitesse 7385 5-port switch */
+#endif
 
-/* I2C */
+#define CONFIG_PCI
+#define CONFIG_RTC_DS1337
 #define CONFIG_HARD_I2C
+#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
 
+/*
+ * Device configurations
+ */
+
+/* I2C */
 #ifdef CONFIG_HARD_I2C
 
 #define CONFIG_MISC_INIT_F
@@ -111,59 +125,40 @@
 
 #endif
 
-#define CONFIG_TSEC_ENET		/* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
+/* Compact Flash */
+#ifdef CONFIG_COMPACT_FLASH
 
-#define PCI_66M
-#ifdef PCI_66M
-#define CONFIG_83XX_CLKIN	66666666	/* in Hz */
-#else
-#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
-#endif
+#define CFG_IDE_MAXBUS		1
+#define CFG_IDE_MAXDEVICE	1
 
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_66M
-#define CONFIG_SYS_CLK_FREQ	66666666
-#else
-#define CONFIG_SYS_CLK_FREQ	33333333
-#endif
-#endif
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	CFG_CF_BASE
+#define CFG_ATA_DATA_OFFSET	0x0000
+#define CFG_ATA_REG_OFFSET	0
+#define CFG_ATA_ALT_OFFSET	0x0200
+#define CFG_ATA_STRIDE		2
 
-#define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
+#define ATA_RESET_TIME	1	/* If a CF card is not inserted, time out quickly */
 
-#undef CFG_DRAM_TEST				/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00003000	/* memtest region */
-#define CFG_MEMTEST_END		0x07100000	/* only has 128M */
+#define CONFIG_DOS_PARTITION
 
-/*
- * DDR Setup
- */
-#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
-#undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#endif
 
 /*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
+ * DDR Setup
  */
-#undef CONFIG_DDR_32BIT
-
-#define CFG_DDR_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
-#undef	CONFIG_DDR_2T_TIMING
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE 		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE 	CFG_DDR_BASE
 #define CFG_83XX_DDR_USES_CS0
+#define CFG_MEMTEST_START	0x1000		/* memtest region */
+#define CFG_MEMTEST_END		0x2000
 
-#ifndef CONFIG_SPD_EEPROM
-/*
- * Manually set up DDR parameters
- */
+#ifdef CONFIG_HARD_I2C
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#endif
+
+#ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
     #define CFG_DDR_SIZE	256		/* Mb */
     #define CFG_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 
@@ -171,46 +166,65 @@
     #define CFG_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
 #endif
 
-/* FLASH on the Local Bus */
+/*
+ *Flash on the Local Bus
+ */
+
 #define CFG_FLASH_CFI				/* use the Common Flash Interface */
 #define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		16		/* FLASH size in MB */
 #define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
+boards, we say we have two, but don't display a message if we find only one. */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
+#define CFG_FLASH_SIZE		16		/* FLASH size in MB */
+#define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
+
+/*
+ * BRx, ORx, LBLAWBARx, and LBLAWARx
+ */
+
+/* Flash */
 
 #define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_V)
 #define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000017	/* 16Mb window bytes */
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE
+#define CFG_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
 
-/* VSC7385 on the Local Bus */
-#define CFG_VSC7385_BASE	0xF8000000	/* start of VSC7385   */
+/* Vitesse 7385 */
 
-#define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
-#define CFG_OR1_PRELIM		(0xFFFE0000 /* 128KB */ | \
-				OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
-				OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#ifdef CONFIG_VSC7385
 
-#define CFG_LBLAWBAR1_PRELIM	CFG_VSC7385_BASE	/* Access window base at VSC7385 base */
-#define CFG_LBLAWAR1_PRELIM	0x80000010		/* Access window size 128K */
+#define CFG_VSC7385_BASE	0xF8000000
 
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-#define CFG_MAX_FLASH_SECT	135		/* sectors per device */
+#define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
+				OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
+#define CFG_LBLAWBAR1_PRELIM	CFG_VSC7385_BASE
+#define CFG_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
 
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#endif
 
-#define CFG_LED_BASE		0xF9000000  /* start of LED and Board ID */
+/* LED */
+
+#define CFG_LED_BASE		0xF9000000
 #define CFG_BR2_PRELIM		(CFG_LED_BASE | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM		(0xFFE00000 /* 2MB */ | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \
-				OR_GPCM_SCY_9 | \
-				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CFG_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+				OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
+				OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Compact Flash */
 
 #ifdef CONFIG_COMPACT_FLASH
 
@@ -219,32 +233,16 @@
 #define CFG_BR3_PRELIM		(CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
 #define CFG_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
 
-#define CFG_LBLAWBAR2_PRELIM	CFG_CF_BASE	/* Window base at flash base + LED & Board ID */
-#define CFG_LBLAWAR2_PRELIM	0x8000000F	/* 64K bytes */
-
-#undef CONFIG_IDE_RESET
-#undef CONFIG_IDE_PREINIT
-
-#define CFG_IDE_MAXBUS		1
-#define CFG_IDE_MAXDEVICE	1
-
-#define CFG_ATA_IDE0_OFFSET	0x0000
-#define CFG_ATA_BASE_ADDR	CFG_CF_BASE
-#define CFG_ATA_DATA_OFFSET	0x0000
-#define CFG_ATA_REG_OFFSET	0
-#define CFG_ATA_ALT_OFFSET	0x0200
-#define CFG_ATA_STRIDE		2
-
-#define ATA_RESET_TIME	1	/* If a CF card is not inserted, time out quickly */
+#define CFG_LBLAWBAR3_PRELIM	CFG_CF_BASE
+#define CFG_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
 
 #endif
 
-#define CONFIG_DOS_PARTITION
-
-#define CFG_MID_FLASH_JUMP	0x7F000000
+/*
+ * U-Boot memory configuration
+ */
 #define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
@@ -253,10 +251,10 @@
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000	     /* End of used area in RAM*/
+#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100	  /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
@@ -272,98 +270,10 @@
 #define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CFG_LBC_LBCR	0x00000000
 
-#undef CFG_LB_SDRAM	/* if board has SRDAM on local bus */
-
-#ifdef CFG_LB_SDRAM
-/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- *    port-size = 32-bits = BR2[19:20] = 11
- *    no parity checking = BR2[21:22] = 00
- *    SDRAM for MSEL = BR2[24:26] = 011
- *    Valid = BR[31] = 1
- *
- * 0	4    8	  12   16   20	 24   28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
-
-#define CFG_LBLAWBAR2_PRELIM	0xF0000000
-#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64M */
-
-#define CFG_BR2_PRELIM		(CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V)
-#define CFG_OR2_PRELIM		(0xFC000000 /* 64 MB */ | \
-				 OR_SDRAM_XAM | \
-				 ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \
-				 ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \
-				 OR_SDRAM_EAD)
-
 #define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
 
 /*
- * LSDMR masks
- */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFEN		\
-				| CFG_LBC_LSDMR_BSMA1516	\
-				| CFG_LBC_LSDMR_RFCR8		\
-				| CFG_LBC_LSDMR_PRETOACT6	\
-				| CFG_LBC_LSDMR_ACTTORW3	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC3		\
-				| CFG_LBC_LSDMR_CL3		\
-				)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
-#endif
-
-/*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
@@ -374,20 +284,16 @@
 #define CFG_NS16550_CLK		get_bus_freq(0)
 
 #define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_BAUDRATE		115200
 
 #define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
 #define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
 
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
-#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_FLAT_TREE
+#define CONFIG_OF_BOARD_SETUP
 
 /* maximum size of the flat tree (8K) */
 #define OF_FLAT_TREE_MAX_SIZE	8192
@@ -397,6 +303,9 @@
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
 
+/*
+ * PCI
+ */
 #ifdef CONFIG_PCI
 
 #define CONFIG_MPC83XX_PCI2
@@ -447,14 +356,18 @@
 
 #endif
 
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66666666	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
+#endif
+
 /* TSEC */
 
 #ifdef CONFIG_TSEC_ENET
 
-#ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI
-#endif
-
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE		/* In case CFG_CMD_MII is specified */
 
@@ -468,6 +381,7 @@
 #endif
 
 #ifdef CONFIG_MPC83XX_TSEC2
+#define CONFIG_HAS_ETH1
 #define CONFIG_MPC83XX_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET	0x25000
 #define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
@@ -479,14 +393,15 @@
 
 #endif
 
-
 /*
  * Environment
  */
+#define CONFIG_ENV_OVERWRITE
+
 #ifndef CFG_RAMBOOT
   #define CFG_ENV_IS_IN_FLASH
-  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-  #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+  #define CFG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
   #define CFG_ENV_SIZE		0x2000
 #else
   #define CFG_NO_FLASH		/* Flash is not usable now */
@@ -533,16 +448,23 @@
 /* Watchdog */
 
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
-#ifdef CONFIG_WATCHDOG
-#define CFG_WATCHDOG_VALUE	0xFFFFFFC3
-#endif
 
 /*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CFG_HUSH_PARSER			/* Use the HUSH parser */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"MPC8349E-mITX> "		/* Monitor Command Prompt */
+#define CONFIG_LOADADDR	200000	/* default location for tftp and bootm */
+
+#ifdef CONFIG_MPC8349ITX
+#define CFG_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
+#endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
     #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -562,15 +484,15 @@
  */
 #define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-/* Cache Configuration */
+/*
+ * Cache Configuration
+ */
 #define CFG_DCACHE_SIZE		32768
 #define CFG_CACHELINE_SIZE	32
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log2 of the above value */
 #endif
 
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST	*/
-
 #define CFG_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
@@ -578,12 +500,12 @@
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 
-#ifdef PCI_64BIT
+#ifdef CFG_LOWBOOT
 #define CFG_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
-	HRCWH_64_BIT_PCI |\
+	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0X00000100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
@@ -596,7 +518,7 @@
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
-	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
 	HRCWH_CORE_ENABLE |\
 	HRCWH_FROM_0XFFF00100 |\
 	HRCWH_BOOTSEQ_DISABLE |\
@@ -606,30 +528,32 @@
 	HRCWH_TSEC2M_IN_GMII )
 #endif
 
-/* System performance */
+/*
+ * System performance
+ */
 #define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
 #define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 #define CFG_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
 #define CFG_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 #define CFG_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
 #define CFG_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
-#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count */
 
-/* System IO Config */
+/*
+ * System IO Config
+ */
 #define CFG_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
 #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
 
-#define CFG_HID0_INIT 0x000000000
-
-#define CFG_HID0_FINAL CFG_HID0_INIT
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	CFG_HID0_INIT
 
 #define CFG_HID2	HID2_HBE
 
-/* DDR @ 0x00000000 */
+/* DDR  */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
-/* PCI @ 0x80000000 */
+/* PCI  */
 #ifdef CONFIG_PCI
 #define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -706,97 +630,72 @@
 #endif
 
 #ifdef CONFIG_MPC83XX_TSEC2
-#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 
-#if 1
-#define CONFIG_IPADDR		10.82.19.159
-#define CONFIG_SERVERIP		10.82.48.106
-#define CONFIG_GATEWAYIP	10.82.19.254
-#define CONFIG_NETMASK		255.255.252.0
-#define CONFIG_NETDEV		eth0
-
-#define CONFIG_HOSTNAME		mpc8349emitx
-#define CONFIG_ROOTPATH		/nfsroot0/u/timur/itx-ltib/rootfs
-#define CONFIG_BOOTFILE		timur/uImage
-
-#define CONFIG_UBOOTPATH	timur/u-boot.bin
-#else
 #define CONFIG_IPADDR		192.168.1.253
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.252.0
 #define CONFIG_NETDEV		eth0
 
+#ifdef CONFIG_MPC8349ITX
 #define CONFIG_HOSTNAME		mpc8349emitx
-#define CONFIG_ROOTPATH		/nfsroot/rootfs
-#define CONFIG_BOOTFILE		uImage
-
-#define CONFIG_UBOOTPATH	u-boot.bin
+#else
+#define CONFIG_HOSTNAME		mpc8349emitxgp
 #endif
 
-#define CONFIG_UBOOTSTART	fe700000
-#define CONFIG_UBOOTEND		fe77ffff
-
-#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
-
-#define CONFIG_BAUDRATE		115200
+/* Default path and filenames */
+#define CONFIG_ROOTPATH		/nfsroot/rootfs
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 
-#undef CONFIG_BOOTCOMMAND
-#ifdef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTDELAY	6
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_FDTFILE		mpc8349emitx.dtb
 #else
-#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_FDTFILE		mpc8349emitxgp.dtb
 #endif
 
+#define CONFIG_BOOTDELAY	0
+
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 
 #define CONFIG_BOOTARGS \
 	"root=/dev/nfs rw" \
 	" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
-	" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
+	" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" 	\
 		MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
 		MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
 	" console=ttyS0," MK_STR(CONFIG_BAUDRATE)
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
-	"tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
-		"erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
-		"cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \
-		"cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \
-	"tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
-		"protect off FEF00000 FEF7FFFF; " \
-		"erase FEF00000 FEF7FFFF; " \
-		"cp.b $loadaddr FEF00000 $filesize; " \
-		"protect on FEF00000 FEF7FFFF; " \
-		"cmp.b $loadaddr FEF00000 $filesize\0" \
-	"tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \
-	"copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
-		"cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0"	\
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
+	"tftpflash=tftpboot $loadaddr $uboot; " 			\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
 	"fdtaddr=400000\0"						\
-	"fdtfile=mpc8349emitx.dtb\0"					\
-	""
+	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
 
 #define CONFIG_NFSBOOTCOMMAND						\
-   "setenv bootargs root=/dev/nfs rw "					\
-      "nfsroot=$serverip:$rootpath "					\
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-      "console=$consoledev,$baudrate $othbootargs;"			\
-   "tftp $loadaddr $bootfile;"						\
-   "tftp $fdtaddr $fdtfile;"						\
-   "bootm $loadaddr - $fdtaddr"
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
+	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND						\
-   "setenv bootargs root=/dev/ram rw "					\
-      "console=$consoledev,$baudrate $othbootargs;"			\
-   "tftp $ramdiskaddr $ramdiskfile;"					\
-   "tftp $loadaddr $bootfile;"						\
-   "tftp $fdtaddr $fdtfile;"						\
-   "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
+	"setenv bootargs root=/dev/ram rw"				\
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
 #undef MK_STR
 #undef XMK_STR
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 8ad6551..d2af0e1 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -100,12 +100,19 @@
 #define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CFG_SDRAM_BASE		CFG_DDR_BASE
 #define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
 #define CFG_83XX_DDR_USES_CS0
 
-#undef	CONFIG_DDR_ECC		/* only for ECC DDR module */
+#define CONFIG_DDR_ECC		/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
 
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CFG_DDRCDR_VALUE	0x80080001
+
 #define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
 #if defined(CONFIG_SPD_EEPROM)
 /*
@@ -117,6 +124,21 @@
  * Manually set up DDR parameters
  */
 #define CFG_DDR_SIZE		256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CFG_DDRCDR		0x80080001
+#define CFG_DDR_CS0_BNDS	0x0000000f
+#define CFG_DDR_CS0_CONFIG	0x80330102
+#define CFG_DDR_TIMING_0	0x00220802
+#define CFG_DDR_TIMING_1	0x38357322
+#define CFG_DDR_TIMING_2	0x2f9048c8
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_CLK_CNTL	0x02000000
+#define CFG_DDR_MODE		0x47d00432
+#define CFG_DDR_MODE2		0x8000c000
+#define CFG_DDR_INTERVAL	0x03cf0080
+#define CFG_DDR_SDRAM_CFG	0x43000000
+#define CFG_DDR_SDRAM_CFG2	0x00401000
+#else
 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
 #define CFG_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 #define CFG_DDR_TIMING_2	0x00000800 /* may need tuning */
@@ -124,6 +146,7 @@
 #define CFG_DDR_MODE		0x20000162 /* DLL,normal,seq,4/2.5 */
 #define CFG_DDR_INTERVAL	0x045b0100 /* page mode */
 #endif
+#endif
 
 /*
  * Memory test
@@ -168,7 +191,7 @@
 #define CFG_FLASH_CFI		/* use the Common Flash Interface */
 #define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CFG_FLASH_SIZE		16 /* FLASH size is 16M */
+#define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
 
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
 #define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
@@ -176,10 +199,12 @@
 #define CFG_BR0_PRELIM	(CFG_FLASH_BASE | /* Flash Base address */ \
 			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 			BR_V)	/* valid */
-#define CFG_OR0_PRELIM		0xfe006ff7 /* 16MB Flash size */
+#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
 #define CFG_MAX_FLASH_BANKS	1 /* number of banks */
-#define CFG_MAX_FLASH_SECT	128 /* sectors per device */
+#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
 
 #undef	CFG_FLASH_CHECKSUM
 
@@ -188,7 +213,7 @@
  */
 #define CFG_BCSR		0xF8000000
 #define CFG_LBLAWBAR1_PRELIM	CFG_BCSR /* Access window base at BCSR base */
-#define CFG_LBLAWAR1_PRELIM	0x8000000E /* Access window size 32K */
+#define CFG_LBLAWAR1_PRELIM	0x8000000F /* Access window size 64K */
 
 #define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
 #define CFG_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
@@ -278,8 +303,8 @@
 /*
  * Windows to access PIB via local bus
  */
-#define CFG_LBLAWBAR3_PRELIM	0xf8008000 /* windows base 0xf8008000 */
-#define CFG_LBLAWAR3_PRELIM	0x8000000f /* windows size 64KB */
+#define CFG_LBLAWBAR3_PRELIM	0xf8010000 /* windows base 0xf8010000 */
+#define CFG_LBLAWAR3_PRELIM	0x8000000e /* windows size 32KB */
 
 /*
  * CS4 on Local Bus, to PIB
@@ -309,6 +334,7 @@
 #define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
 #define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
 #ifdef	CFG_HUSH_PARSER
@@ -324,6 +350,7 @@
 
 #define OF_CPU			"PowerPC,8360@0"
 #define OF_SOC			"soc8360@e0000000"
+#define OF_QE			"qe@e0100000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc8360@e0000000/serial@4500"
 
@@ -609,7 +636,7 @@
    "ramdiskaddr=1000000\0"						\
    "ramdiskfile=ramfs.83xx\0"						\
    "fdtaddr=400000\0"							\
-   "fdtfile=mpc8349emds.dtb\0"						\
+   "fdtfile=mpc8360emds.dtb\0"						\
    ""
 
 #define CONFIG_NFSBOOTCOMMAND						\
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 728083b..ed03577 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -57,17 +57,6 @@
  */
 #define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
 
-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
 /* board pre init: do not call, nothing to do */
 #undef CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
new file mode 100644
index 0000000..65aac5c
--- /dev/null
+++ b/include/configs/sbc8349.h
@@ -0,0 +1,734 @@
+/*
+ * WindRiver SBC8349 U-Boot configuration file.
+ * Copyright (c) 2006, 2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on the MPC8349EMDS config.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * sbc8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC834X		1	/* MPC834X family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
+
+#undef CONFIG_PCI
+/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+
+#define CFG_IMMR		0xE0000000
+
+#undef CFG_DRAM_TEST				/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00000000	/* memtest region */
+#define CFG_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#define CFG_83XX_DDR_USES_CS0		/* WRS; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x52		/* DDR DIMM */
+
+#else
+/*
+ * Manually set up DDR parameters
+ * NB: manual DDR setup untested on sbc834x
+ */
+#define CFG_DDR_SIZE		256		/* MB */
+#define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CFG_DDR_TIMING_1	0x36332321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
+#else
+/* the default burst length is 4 - for 64-bit data path */
+#define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0x10000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* flash size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
+				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+				BR_V)			/* valid */
+
+#define CFG_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP	0x7F000000
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000			/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR	0x00000000
+
+#undef CFG_LB_SDRAM	/* if board has SDRAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CFG_LBLAWBAR2_PRELIM	0xF0000000
+#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64M */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+#define CFG_OR2_PRELIM	0xFC006901
+
+#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
+				| CFG_LBC_LSDMR_BSMA1516	\
+				| CFG_LBC_LSDMR_RFCR8		\
+				| CFG_LBC_LSDMR_PRETOACT6	\
+				| CFG_LBC_LSDMR_ACTTORW3	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC3		\
+				| CFG_LBC_LSDMR_CL3		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8349@0"
+#define OF_SOC			"soc8349@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#define CFG_I2C1_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+#define CFG_I2C_OFFSET		CFG_I2C2_OFFSET
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MMIO_BASE	0x90000000
+#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xE2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CFG_PCI2_MEM_BASE	0xA0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_MMIO_BASE	0xB0000000
+#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
+#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xE2100000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_MPC83XX_TSEC1	1
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2	1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_BCM5421S	1
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C		\
+				)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C		\
+				| CFG_CMD_MII		\
+				)
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#if 1 /*528/264*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*396/132*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_3X1)
+#elif 0 /*264/132*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*132/132*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#elif 0 /*264/264 */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#endif
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+
+/* #define CFG_HID0_FINAL		(\
+	HID0_ENABLE_INSTRUCTION_CACHE |\
+	HID0_ENABLE_M_BIT |\
+	HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT1L	(0)
+#define CFG_IBAT1U	(0)
+#define CFG_IBAT2L	(0)
+#define CFG_IBAT2U	(0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L	(0)
+#define CFG_IBAT3U	(0)
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR		00:a0:1e:a0:13:8d
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:a0:1e:a0:13:8e
+#endif
+
+#define CONFIG_IPADDR		192.168.1.234
+
+#define CONFIG_HOSTNAME		SBC8349
+#define CONFIG_ROOTPATH		/tftpboot/rootfs
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=sbc8349\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"		\
+	"update=protect off fff00000 fff3ffff; "			\
+		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0"	\
+	"upd=run load;run update\0"					\
+	"fdtaddr=400000\0"						\
+	"fdtfile=sbc8349.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */