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authorWolfgang Denk <wd@denx.de>2008-06-11 22:48:09 +0200
committerWolfgang Denk <wd@denx.de>2008-06-11 22:48:09 +0200
commit1a5017601f6d17caedaa2bf069485d3e4155f1c0 (patch)
tree342b39d2a55eb4ebaf8b772bc8b74db4318d5eb7 /include/configs
parentcdeb62e20d94005f2e80604fda03b498c3a6f704 (diff)
parent79b51ff8205f0354d5300570614c1d2db499679c (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-mips
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/dbau1x00.h14
-rw-r--r--include/configs/gth2.h8
-rw-r--r--include/configs/incaip.h4
-rw-r--r--include/configs/pb1x00.h12
-rw-r--r--include/configs/purple.h3
-rw-r--r--include/configs/qemu-mips.h4
-rw-r--r--include/configs/tb0229.h4
7 files changed, 31 insertions, 18 deletions
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index b2f606f..0e10396 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -30,21 +30,21 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X00 1
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
-#define CONFIG_AU1000 1
+#define CONFIG_SOC_AU1000 1
#else
#ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100 1
+#define CONFIG_SOC_AU1100 1
#else
#ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500 1
+#define CONFIG_SOC_AU1500 1
#else
#ifdef CONFIG_DBAU1550
/* Cabernet */
-#define CONFIG_AU1550 1
+#define CONFIG_SOC_AU1550 1
#else
#error "No valid board set"
#endif
@@ -148,7 +148,9 @@
#error "Invalid CPU frequency - must be multiple of 12!"
#endif
-#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000)
+
+#define CFG_HZ 1000
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index c2a50c1..c2d6ca7 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -30,9 +30,9 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_GTH2 1
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-#define CONFIG_AU1000 1
+#define CONFIG_SOC_AU1000 1
#define CONFIG_MISC_INIT_R 1
@@ -118,7 +118,9 @@
#define CFG_MHZ 500
-#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000)
+
+#define CFG_HZ 1000
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 5ca00b3..2e4ee66 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -118,7 +118,9 @@
#define CFG_BOOTPARAMS_LEN 128*1024
-#define CFG_HZ (incaip_get_cpuclk() / 2)
+#define CFG_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2)
+
+#define CFG_HZ 1000
#define CFG_SDRAM_BASE 0x80000000
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 810e0f0..2caa641 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -30,16 +30,16 @@
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_PB1X00 1
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_PB1000
-#define CONFIG_AU1000 1
+#define CONFIG_SOC_AU1000 1
#else
#ifdef CONFIG_PB1100
-#define CONFIG_AU1100 1
+#define CONFIG_SOC_AU1100 1
#else
#ifdef CONFIG_PB1500
-#define CONFIG_AU1500 1
+#define CONFIG_SOC_AU1500 1
#else
#error "No valid board set"
#endif
@@ -81,7 +81,9 @@
#define CFG_BOOTPARAMS_LEN 128*1024
-#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ 396000000
+
+#define CFG_HZ 1000
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
diff --git a/include/configs/purple.h b/include/configs/purple.h
index 1be4e05..ef92637 100644
--- a/include/configs/purple.h
+++ b/include/configs/purple.h
@@ -114,7 +114,8 @@
#define CFG_PROMPT "PURPLE # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_HZ (CPU_CLOCK_RATE/2)
+#define CFG_MIPS_TIMER_FREQ (CPU_CLOCK_RATE/2)
+#define CFG_HZ 1000
#define CFG_MAXARGS 16 /* max number of command args*/
#define CFG_LOAD_ADDR 0x80500000 /* default load address */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index d6bcc8e..3dfd218 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -120,7 +120,9 @@
#define CFG_MHZ 132
-#define CFG_HZ (CFG_MHZ * 1000000)
+#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000)
+
+#define CFG_HZ 1000
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
index dadf5d3..fc2357d 100644
--- a/include/configs/tb0229.h
+++ b/include/configs/tb0229.h
@@ -122,7 +122,9 @@
#define CFG_BOOTPARAMS_LEN 128*1024
-#define CFG_HZ (CPU_TCLOCK_RATE/4)
+#define CFG_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4)
+
+#define CFG_HZ 1000
#define CFG_SDRAM_BASE 0x80000000