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| author | Thierry Reding <treding@nvidia.com> | 2013-07-18 12:13:40 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-08-19 15:31:37 -0700 |
| commit | 0d79f4f490352f6e1500cdd12a3b0e8b17265bde (patch) | |
| tree | 22fa69c5699349157e4c5848e84b13a9b2d6736c /include/configs | |
| parent | 9ed887caecb9ecb0c68773a1870d143b9f28d3da (diff) | |
| download | u-boot-imx-0d79f4f490352f6e1500cdd12a3b0e8b17265bde.zip u-boot-imx-0d79f4f490352f6e1500cdd12a3b0e8b17265bde.tar.gz u-boot-imx-0d79f4f490352f6e1500cdd12a3b0e8b17265bde.tar.bz2 | |
ARM: tegra: Make cache line size SoC specific
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/tegra-common.h | 2 | ||||
| -rw-r--r-- | include/configs/tegra114-common.h | 3 | ||||
| -rw-r--r-- | include/configs/tegra20-common.h | 3 | ||||
| -rw-r--r-- | include/configs/tegra30-common.h | 3 |
4 files changed, 9 insertions, 2 deletions
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ccd68a1..0aac14e 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/tegra.h> /* get chip and board defs */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 44e98e5..c3de9a9 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -18,6 +18,9 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * NS16550 Configuration */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index d5e9ee4..b009a31 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -9,6 +9,9 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 5ac8816..99acbfd 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,6 +9,9 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ |