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authorWolfgang Denk <wd@pollux.denx.de>2006-07-22 21:45:49 +0200
committerWolfgang Denk <wd@pollux.denx.de>2006-07-22 21:45:49 +0200
commitfd27996dacd308849e30f67da49ba068a7f68aaa (patch)
treec7d85ed14bd21e9845ed181017d4340d606418b3 /include/configs
parent135ae0062f358c644d3c6a40adea3e2de6269157 (diff)
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Add support for 256 MB SDRAM on CPU87
Patch by Josef Wagner, 25 Nov 2005
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/CPU87.h24
1 files changed, 21 insertions, 3 deletions
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 9a98e5c..7a1dada 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -455,7 +455,7 @@
#define CFG_MIN_AM_MASK 0xC0000000
/*
- * we use the same values for 32 MB and 128 MB SDRAM
+ * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
* refresh rate = 7.68 uS (100 MHz Bus Clock)
*/
@@ -510,6 +510,24 @@
PSDMR_WRC_1C |\
PSDMR_CL_2)
+ /* SDRAM initialization values for 10-column chips
+ */
+#define CFG_OR2_10COL (CFG_MIN_AM_MASK |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI1_A4 |\
+ ORxS_NUMR_13)
+
+#define CFG_PSDMR_10COL (PSDMR_PBI |\
+ PSDMR_SDAM_A17_IS_A5 |\
+ PSDMR_BSMA_A13_A15 |\
+ PSDMR_SDA10_PBI1_A6 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
/*
* Init Memory Controller:
*
@@ -588,9 +606,9 @@
BRx_MS_SDRAM_P |\
BRx_V)
-#define CFG_OR2_PRELIM CFG_OR2_9COL
+#define CFG_OR2_PRELIM CFG_OR2_8COL
-#define CFG_PSDMR CFG_PSDMR_9COL
+#define CFG_PSDMR CFG_PSDMR_8COL
#endif /* CFG_RAMBOOT */
/* Bank 3 - Dual Ported SRAM