diff options
| author | wdenk <wdenk> | 2005-03-31 23:44:33 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2005-03-31 23:44:33 +0000 |
| commit | ef2807c667a91135fbb91b805b852ccfbff03587 (patch) | |
| tree | a271ce0de68dfef93e4106bb8d5f9363f6d9ae33 /include/configs | |
| parent | 83e40ba75d7f8d0c2e2ecdd203db96ccd79a0340 (diff) | |
| download | u-boot-imx-ef2807c667a91135fbb91b805b852ccfbff03587.zip u-boot-imx-ef2807c667a91135fbb91b805b852ccfbff03587.tar.gz u-boot-imx-ef2807c667a91135fbb91b805b852ccfbff03587.tar.bz2 | |
Patch by Steven Scholz, 13 Dec 2004:
Remove duplicated code by merging memsetup.S files for
at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/at91rm9200dk.h | 31 | ||||
| -rw-r--r-- | include/configs/cmc_pu2.h | 32 |
2 files changed, 63 insertions, 0 deletions
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 58e2045..8146fe7 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -47,6 +47,37 @@ /* define this to include the functionality of boot.bin in u-boot */ #undef CONFIG_BOOTBINFUNC +#ifdef CONFIG_BOOTBINFUNC +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* * Size of malloc() pool */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index e87e318..a9742c1 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -52,6 +52,38 @@ #define CONFIG_BOOTBINFUNC #endif +#ifdef CONFIG_BOOTBINFUNC +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x202CBE04 /* 207.360 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif + /* * Size of malloc() pool */ |