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authorWolfgang Denk <wd@denx.de>2011-11-08 00:38:52 +0100
committerWolfgang Denk <wd@denx.de>2011-11-08 00:38:52 +0100
commit688d8f33f27ea596efb6632388ee60360996eed0 (patch)
tree961e812048557d4ac7062e6a7387f543e7d634af /include/configs
parent7ba6d591b5a6ec4ed502de7d94ff726bce13fe61 (diff)
parent2026a119512a9cced2957221e83fef92b8211d26 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: Arm: re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board arm: jadecpu: Readd MACH_TYPE_JADECPU at91: defined mach-types for otc570 board in board config file at91: defined mach-types for meesc board in board config file mx31pdk: Enable D and I caches ehci-mxc: remove incorrect comment README: Fix supported i.MX SoC list for CONFIG_MXC_SPI mx53: Turn off child clocks before reconfigure perclk_root qong: enable support for compressed images imx: imx31_phycore.h: fix checkpatch warnings vision2: Remove unused get_board_rev function mx53smd: Remove unused get_board_rev function mx53ard: Remove unused get_board_rev function mx53evk: Remove unused get_board_rev function mx53evk: Add RTC support mx53loco: Remove unused get_board_rev function mx53evk: Remove unneeded '1' from mx53evk.h OMAP3: mvblx: Initial support for mvBlueLYNX-X ARM: dig297: Define MACH_TYPE_OMAP3_CPS and CONFIG_MACH_TYPE omap3: mem: Move comments next to definitions omap3: mem: Clean-up whitespaces omap3: mem: Define and use common macros Davinci: ea20: added PREBOOT to configuration Davinci: ea20: added I2C support Davinci: ea20: added video support VIDEO: davinci: add framebuffer to da8xx ARM: Davinci: added missing registers to hardware.h Davinci: ea20: add gpios for LCD backlight control Davinci: ea20: add gpio for keeping power on in board_late_init Davinci: ea20: Add default U-Boot environment Davinci: ea20: Add early init to get early output from console Davinci: ea20: Add NAND support Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console Davinci: ea20: set console on UART0 arm, davinci: add cam_enc_4xx support arm926ejs, davinci: add missing spi defines for dm365 arm926ejs, davinci: add cpuinfo for dm365 arm, davinci: add lowlevel function for dm365 soc arm, davinci: add header files for dm365 spl, nand: add 4bit HW ecc oob first nand_read_page function arm, davinci: add support for new spl framework spl: add option for adding post memory test to the SPL framework net, davinci_emac: make clock divider in MDIO control register configurable arm, usb, davinci: make USBPHY_CTL register configurable usb, davinci: add enable_vbus() weak function omap3evm: fix errors caused by multiple definitions omap3evm: Add (quick) configuration for NAND only omap3evm: Add (quick) configuration for MMC/SD only omap3evm: move common config options to new file omap3evm: Prepare to split configuration omap3evm: Reorder related config options omap/spl: actually enable the console davinci_emac: compilation fix, phy is array now omap3evm: Set environment variable 'ethaddr' arm, arm926: fix missing symbols in NAND_SPL mode arm, davinci: Add function lpsc_syncreset() arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD arm/km: portl2 environment address update to P1B arm/km: adapt bootcounter evaluation arm/km: enable jffs2 cmds arm/km: trigger reconfiguration for the Xilinx FPGA arm/km: add boardid and hwkey to kernel command line ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards netspace_v2: enable I2C EEPROM support netspace_v2: fix SDRAM configuration armada100: define CONFIG_SYS_CACHELINE_SIZE pantheon: define CONFIG_SYS_CACHELINE_SIZE kirkwood: define CONFIG_SYS_CACHELINE_SIZE kirkwood: drop empty asm-offsets.s file arm/km/mgcoge3un: enhance "waitforne" feature arm/km: add variable waitforne to mgcoge3un gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared ARM: dreamplug: fix compilation ARM: DockStar: fix compilation ARM: netspace_v2: fix warnings am335x: Drop board_sysinfo struct am335x: Temporarily add MACH_TYPE define misc:pmic:samsung Enable PMIC driver at C210 Universal target dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target smdkv310: use macro for mmc data read function address smdkv310: use spl framework for mmc spl SMDKV310: use get_ram_size() to validate dram size SMDKV310: Initialize board id using CONFIG_MACH_TYPE ORIGEN : use absolute paths and fix tool naming ORIGEN : enable device tree support MX25: tx25: Fix building due to missing MACH_TYPE mx31: Add board support for HALE TT-01 mx31: add ESD control registers mx31: define pins and init for UART2 and CSPI3 MX35: add support for flea3 board MX51: vision2: add MACH_TYPE in config file vision2: Remove unused header file mx51evk: Remove unused get_board_rev function mx51evk: Remove unneeded '1' from mx51evk.h I2C: Fix mxc_i2c.c problem on imx31_phycore mx35pdk: Add RTC support mx51evk: Use GPIO API for configuring the IOMUX mx51evk: Add RTC support rtc: Make mc13783-rtc driver generic qong: remove unneeded IOMUX settings qong: Use mx31_set_gpr to setup USBH2 pins mx31: Introduce mx31_set_gpr function mx31pdk: Add MC13783 PMIC support qong: remove unneeded "1" from qong.h misc: pmic: fix regression in pmic_fsl.c (SPI) mx5 configs: CONFIG_PRIME should really be CONFIG_ETHPRIME MX35: Drop unnecessary prototypes from imx-regs.h I2C: added I2C-2 and I2C-3 to MX35 MX35: factorize common assembly code MX35: add reset cause as provided by other i.MX MX35: add pins definition for UART3 MX35: added ESDC structure to imx-regs
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/am335x_evm.h1
-rw-r--r--include/configs/cam_enc_4xx.h453
-rw-r--r--include/configs/dig297.h8
-rw-r--r--include/configs/ea20.h126
-rw-r--r--include/configs/eb_cpux9k2.h2
-rw-r--r--include/configs/efikamx.h2
-rw-r--r--include/configs/flea3.h286
-rw-r--r--include/configs/gplugd.h12
-rw-r--r--include/configs/imx31_litekit.h2
-rw-r--r--include/configs/imx31_phycore.h153
-rw-r--r--include/configs/jadecpu.h4
-rw-r--r--include/configs/km/km_arm.h9
-rw-r--r--include/configs/km_kirkwood.h3
-rw-r--r--include/configs/meesc.h8
-rw-r--r--include/configs/mgcoge3un.h2
-rw-r--r--include/configs/mx31ads.h2
-rw-r--r--include/configs/mx31pdk.h2
-rw-r--r--include/configs/mx35pdk.h2
-rw-r--r--include/configs/mx51evk.h14
-rw-r--r--include/configs/mx53ard.h3
-rw-r--r--include/configs/mx53evk.h19
-rw-r--r--include/configs/mx53loco.h3
-rw-r--r--include/configs/mx53smd.h3
-rw-r--r--include/configs/netspace_v2.h18
-rw-r--r--include/configs/omap3_evm.h331
-rw-r--r--include/configs/omap3_evm_common.h292
-rw-r--r--include/configs/omap3_evm_quick_mmc.h91
-rw-r--r--include/configs/omap3_evm_quick_nand.h79
-rw-r--r--include/configs/omap3_mvblx.h313
-rw-r--r--include/configs/origen.h3
-rw-r--r--include/configs/otc570.h7
-rw-r--r--include/configs/portl2.h6
-rw-r--r--include/configs/qong.h41
-rw-r--r--include/configs/s5p_goni.h2
-rw-r--r--include/configs/s5pc210_universal.h19
-rw-r--r--include/configs/smdkv310.h8
-rw-r--r--include/configs/tt01.h254
-rw-r--r--include/configs/tx25.h6
-rw-r--r--include/configs/vision2.h6
39 files changed, 2194 insertions, 401 deletions
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index b471c9b..26a3c96 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -32,6 +32,7 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 * 1024))
#define CONFIG_SYS_PROMPT "AM335X# "
#define CONFIG_SYS_NO_FLASH
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_CMD_ASKENV
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
new file mode 100644
index 0000000..a21d448
--- /dev/null
+++ b/include/configs/cam_enc_4xx.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS /* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SOC_DM365
+
+#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
+
+#define CONFIG_HOSTNAME cam_enc_4xx
+
+#define BOARD_LATE_INIT
+#define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
+#define DDR_4BANKS /* 4-bank DDR2 (256MB) */
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Serial Driver info: UART0 for console */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 0x01c20000
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
+#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_RESET_PHY_R
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+
+/* SPI support */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
+#define CONFIG_SF_DEFAULT_SPEED 3000000
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_CMD_SF
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x0
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
+#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
+
+#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/* Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT "2m(bootloader)ro,"
+#endif
+
+#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
+#define PART_REST "-(filesystem)"
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE (0x800)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (0x20000)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POST_MEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
+
+#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE 12320
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_TEXT_BASE 0x81080000
+#endif
+
+#define CONFIG_SYS_NAND_BASE 0x02000000
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 0x200
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL (40)
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we can write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER 5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+/*
+ * Post tests for memory testing
+ */
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY
+#define _POST_WORD_ADDR 0x0
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+
+/*
+ * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
+ * done in board_init_f from c code.
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* for UBL header */
+#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
+#define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
+#define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
+#define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
+#define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
+/* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
+/*
+ * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
+ * interface clk)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
+/* POST DIV 680/2 = 340Mhz -> VPSS */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
+/* POST DIV 680/9 = 75.6 Mhz -> VENC */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
+/*
+ * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
+ * down to 340 Mhz)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
+/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
+/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
+
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
+/* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
+/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
+/* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
+
+/*
+ * READ LATENCY 7 (CL + 2)
+ * CONFIG_PWRDNEN = 1
+ * CONFIG_EXT_STRBEN = 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
+ | DV_DDR_PHY_EXT_STRBEN \
+ | DV_DDR_PHY_PWRDNEN \
+ | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+/*
+ * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
+ * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
+ * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
+ * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
+ * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
+ | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
+ | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
+ | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
+ | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
+ | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
+ | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
+ | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
+ | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
+ * T_XP = tCKE - 1 = 3 - 2
+ * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
+ * T_XSRD = txsrd - 1 = 200 - 1
+ * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_CKE = tcke - 1 = 3 - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
+ | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
+ | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
+ | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
+ | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+/* PR_OLD_COUNT = 0xfe */
+#define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
+/* refresh rate = 0x768 */
+#define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
+
+#define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
+ | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
+ | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
+ | (5 << DV_DDR_SDCR_CL_SHIFT) \
+ | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
+ | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
+ | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
+ | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
+ | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
+
+#define CONFIG_SYS_DM36x_AWCCR 0xff
+#define CONFIG_SYS_DM36x_AB1CR 0x40400204
+#define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
+
+/* All Video Inputs */
+#define CONFIG_SYS_DM36x_PINMUX0 0x00000000
+/*
+ * All Video Outputs,
+ * GPIO 86, 87 + 90 0x0000f030
+ */
+#define CONFIG_SYS_DM36x_PINMUX1 0x00530002
+#define CONFIG_SYS_DM36x_PINMUX2 0x00001815
+/*
+ * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+ * GPIO 25 0x60000000
+ */
+#define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
+/*
+ * MMC/SD0 instead of MS, SPI0
+ * GPIO 34 0x0000c000
+ */
+#define CONFIG_SYS_DM36x_PINMUX4 0x00002655
+
+/*
+ * Default environment settings
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
+/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
+#define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
+/*
+ * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
+ * CONFIG_SYS_NAND_PAGE_SIZE))
+ */
+#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
+ "load=tftp ${u_boot_addr_r} ${uboot}\0" \
+ "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
+ "writeheader=nandrbl rbl;nand erase 80000 ${pagesz};" \
+ "nand write ${u_boot_addr_r} 80000 ${pagesz};" \
+ "nandrbl uboot\0" \
+ "writenand_spl=nandrbl rbl;nand erase a0000 3000;" \
+ "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
+ " a0000 3000;nandrbl uboot\0" \
+ "writeuboot=nandrbl uboot;" \
+ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \
+ ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
+ " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
+ "update=run load writenand_spl writeuboot\0" \
+ "bootcmd=run bootcmd\0" \
+ "rootpath=/opt/eldk-arm/arm\0" \
+ "\0"
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
+ USBPHY_PHY24MHZ)
+
+#define CONFIG_CMD_USB /* include support for usb cmd */
+#define CONFIG_USB_STORAGE /* MSC class support */
+#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
+
+#undef DAVINCI_DM365EVM
+#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
+#define PINMUX4_USBDRVBUS_BITSET 0x2000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index 3a05c82..9baf415 100644
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -32,6 +32,14 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_OMAP3_CPS
+#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
+#else
+#define MACH_TYPE_OMAP3_CPS 2751
+#endif
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
+
/*
* High Level Configuration Options
*/
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 201e6b5..74fec3f 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -28,7 +28,12 @@
*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_USE_SPIFLASH
+#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOARD_EARLY_INIT_F
+#define BOARD_LATE_INIT
+#define CONFIG_VIDEO
+#define CONFIG_PREBOOT
/*
* SoC Configuration
@@ -47,7 +52,7 @@
/*
* Memory Info
*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
@@ -67,7 +72,7 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
@@ -83,6 +88,13 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/*
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
@@ -99,11 +111,22 @@
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_OFFSET 0x80000
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#define CONFIG_SYS_NO_FLASH
#endif
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#endif
+
/*
* U-Boot general configuration
*/
@@ -143,6 +166,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_I2C
#ifndef CONFIG_DRIVER_TI_EMAC
#undef CONFIG_CMD_NET
@@ -151,7 +175,8 @@
#undef CONFIG_CMD_PING
#endif
-#ifdef CONFIG_USE_NAND
+/* NAND Setup */
+#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
@@ -163,8 +188,20 @@
#define CONFIG_RBTREE
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
+
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 2
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
+/* SPI Flash */
#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
@@ -173,7 +210,7 @@
#define CONFIG_CMD_SAVEENV
#endif
-#if !defined(CONFIG_USE_NAND) && \
+#if !defined(CONFIG_SYS_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
@@ -187,4 +224,83 @@
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+
+#define CONFIG_HOSTNAME ea20
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "as=3\0" \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "rfsbargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rfsbpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "mtdids=nand0=davinci_nand.0\0" \
+ "mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel)," \
+ "8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0" \
+ "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
+ "ubi.mtd=${as} root=ubi0:rootfs\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=${consoledev},${baudrate}n8\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
+ "consoledev=ttyS0\0" \
+ "loadaddr=c0000014\0" \
+ "memory=32M\0" \
+ "kernel_addr_r=c0700000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc addmem;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run rfsbargs addip addtty addmtd addmisc addmem; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "ubifsload ${kernel_addr_r} /boot/uImage;" \
+ "ubifsumount; run nandargs addip addtty " \
+ "addmtd addmisc addmem;bootm ${kernel_addr_r}\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load_magic=if sf probe 0;then sf " \
+ "read c0000000 0x10000 0x60000;fi\0" \
+ "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "if ubifsload c0000014 /boot/u-boot.bin;" \
+ "then mw c0000008 ${filesize};else echo Error reading " \
+ "u-boot from nand!;fi\0" \
+ "load_net=if sf probe 0;then sf read c0000000 0x10000 0x60000;" \
+ "tftp c0000014 ${u-boot};" \
+ "mw c0000008 ${filesize};" \
+ "fi\0" \
+ "upd=if sf probe 0;then sf erase 10000 60000;" \
+ "sf write c0000000 10000 60000;" \
+ "fi\0" \
+ "ubootupd_net=if run load_net;then echo Updating u-boot;" \
+ "if run upd; then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
+ "bootcmd=run net_nfs\0"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 4324172..b08de4a 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -41,6 +41,8 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F
+#define MACH_TYPE_EB_CPUX9K2 1977
+#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
/*--------------------------------------------------------------------------*/
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index b507786..a07c8b5 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -132,7 +132,7 @@
#define CONFIG_FSL_PMIC_CLK 25000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
#endif
/*
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..d88c578
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3 3668
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1)," \
+ "196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 24bf767..9813309 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -32,6 +32,16 @@
#define __CONFIG_GPLUGD_H
/*
+ * FIXME: fix for error caused due to recent update to mach-types.h
+ */
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_SHEEVAD
+#error "MACH_TYPE_SHEEVAD has been defined properly, please remove this."
+#else
+#define MACH_TYPE_SHEEVAD 2625
+#endif
+
+/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nMarvell-gplugD"
@@ -42,7 +52,7 @@
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
#define CONFIG_ARMADA100 1 /* SOC Family Name */
#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
-#define CONFIG_MACH_SHEEVAD /* Machine type */
+#define CONFIG_MACH_TYPE MACH_TYPE_SHEEVAD /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_TEXT_BASE 0x00f00000
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 89e71c0..1455ea2 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -81,7 +81,7 @@
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index f4bfee4..1b75197 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -30,25 +30,18 @@
#include <asm/arch/imx-regs.h>
- /* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
+/* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 /* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ 26000000
#define CONFIG_MX31_CLK32 32000
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-/* Temporarily disabled */
-#if 0
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-#endif
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
/*
* Size of malloc() pool
@@ -59,14 +52,14 @@
* Hardware drivers
*/
-#define CONFIG_HARD_I2C 1
-#define CONFIG_I2C_MXC 1
-#define CONFIG_SYS_I2C_MX31_PORT2 1
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX31_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
-#define CONFIG_MXC_UART 1
-#define CONFIG_SYS_MX31_UART1 1
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX31_UART1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -86,42 +79,60 @@
#define CONFIG_BOOTDELAY 3
-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
+#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
+ "1536k(kernel),-(root)"
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.23.168
#define CONFIG_SERVERIP 192.168.23.2
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
- "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
- "bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2 rootfstype=jffs2" \
- "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)" \
- "bootcmd=run bootcmd_net\0" \
- "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 $(uimage); bootm\0" \
- "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x80000000\0" \
- "unlock=yes\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "prg_uboot=tftpboot 0x80000000 $(uboot); protect off 0xa0000000 +0x20000; erase 0xa0000000 +0x20000; cp.b 0x80000000 0xa0000000 $(filesize)\0" \
- "prg_kernel=tftpboot 0x80000000 $(uimage); erase 0xa0040000 +0x180000; cp.b 0x80000000 0xa0040000 $(filesize)\0" \
- "prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
- "videomode=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:1241513985,vmode:0\0"
-
-
-#define CONFIG_SMC911X 1
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootargs_flash=setenv bootargs $(bootargs) " \
+ "root=/dev/mtdblock2 rootfstype=jffs2\0" \
+ "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
+ "tftpboot 0x80000000 $(uimage);bootm\0" \
+ "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
+ "bootm 0x80000000\0" \
+ "unlock=yes\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "prg_uboot=tftpboot 0x80000000 $(uboot);" \
+ "protect off 0xa0000000 +0x20000;" \
+ "erase 0xa0000000 +0x20000;" \
+ "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
+ "prg_kernel=tftpboot 0x80000000 $(uimage);" \
+ "erase 0xa0040000 +0x180000;" \
+ "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
+ "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
+ "erase 0xa01c0000 0xa1ffffff;" \
+ "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
+ "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
+ "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
+ "sync:1241513985,vmode:0\0"
+
+
+#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE 0xa8000000
-#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_32_BIT
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "uboot> "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x10000
@@ -130,21 +141,21 @@
#define CONFIG_SYS_HZ 1000
-#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_CMDLINE_EDITING
-/*-----------------------------------------------------------------------
+/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-/*-----------------------------------------------------------------------
+/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_TEXT_BASE 0xA0000000
@@ -156,33 +167,37 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_GBL_DATA_OFFSET)
-/*-----------------------------------------------------------------------
+/*
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE 0xa0000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
-#define CONFIG_ENV_SIZE 4096
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
+#define CONFIG_ENV_SIZE 4096
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
-/*-----------------------------------------------------------------------
+/*
* CFI FLASH driver setup
*/
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+/*
+ * Timeout for Flash Erase and Flash Write
+ * timeout values are in ticks
+ */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
/*
* JFFS2 partitions
@@ -196,11 +211,11 @@
#define CONFIG_MXC_GPIO
-#define CONFIG_HARD_SPI 1
-#define CONFIG_MXC_SPI 1
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
#define CONFIG_CMD_SPI
-#define CONFIG_S6E63D6 1
+#define CONFIG_S6E63D6
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
index a239efc..f72ee02 100644
--- a/include/configs/jadecpu.h
+++ b/include/configs/jadecpu.h
@@ -37,6 +37,10 @@
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
+#define MACH_TYPE_JADECPU 2636
+
+#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
+
/*
* Environment settings
*/
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index c117943..700124c 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -36,6 +36,9 @@
#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H
+/* We got removed from Linux mach-types.h */
+#define MACH_TYPE_KM_KIRKWOOD 2255
+
/*
* High Level Configuration Options (easy to change)
*/
@@ -45,6 +48,8 @@
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
+#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
+
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
@@ -69,7 +74,8 @@
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
- "bootcountaddr=${bootcountaddr} ${mtdparts}"
+ "bootcountaddr=${bootcountaddr} ${mtdparts}" \
+ " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - -\0" \
@@ -254,7 +260,6 @@ int get_scl(void);
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
#undef CONFIG_FLASH_CFI_MTD
-#undef CONFIG_CMD_JFFS2
#undef CONFIG_JFFS2_CMDLINE
#endif
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index e51b270..ed36124 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -54,4 +54,7 @@
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN 39
+
#endif /* _CONFIG_KM_KIRKWOOD */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index a2b55d5..ea40290 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -45,6 +45,14 @@
*/
#define CONFIG_SYS_TEXT_BASE 0x20002000
+/*
+ * since a number of boards are not being listed in linux
+ * arch/arm/tools/mach-types any more, the mach-types have to be
+ * defined here
+ */
+#define MACH_TYPE_MEESC 2165
+#define MACH_TYPE_ETHERCAN2 2407
+
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h
index ac01a31..797b0df 100644
--- a/include/configs/mgcoge3un.h
+++ b/include/configs/mgcoge3un.h
@@ -76,6 +76,8 @@
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
+#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
+
/*
* PCIe port not used on mgcoge3un
*/
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index c9d80ef..7e011ae 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -78,7 +78,7 @@
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 2e5cde5..4253c3e 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -79,7 +79,7 @@
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 79bae56..32ed609 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -73,6 +73,7 @@
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
+#define CONFIG_RTC_MC13XXX
/*
* MFD MC9SDZ60
@@ -111,6 +112,7 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_CMD_DATE
#define CONFIG_BOOTDELAY 3
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 028a842..7c7544f 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -41,12 +41,11 @@
* increase in the final file size: 144260 vs. 109536 Bytes.
*/
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
-#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_LIBFDT
#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
/*
@@ -79,6 +78,7 @@
#define CONFIG_FSL_PMIC_CLK 2500000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
+#define CONFIG_RTC_MC13XXX
/*
* MMC Configs
@@ -124,9 +124,11 @@
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_DATE
+
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 3e99031..15dfcb4 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -34,7 +34,6 @@
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -90,7 +89,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "smc911x"
+#define CONFIG_ETHPRIME "smc911x"
/*Support LAN9217*/
#define CONFIG_SMC911X
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 4703248..7c49136 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -33,12 +33,11 @@
#include <asm/arch/imx-regs.h>
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
-#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_LIBFDT
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
@@ -51,9 +50,9 @@
#define CONFIG_SYS_MX53_UART1
/* I2C Configs */
-#define CONFIG_CMD_I2C 1
-#define CONFIG_HARD_I2C 1
-#define CONFIG_I2C_MXC 1
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
@@ -63,6 +62,7 @@
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
+#define CONFIG_RTC_MC13XXX
/* MMC Configs */
#define CONFIG_FSL_ESDHC
@@ -88,6 +88,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
+#define CONFIG_CMD_DATE
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -102,7 +103,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index c3e4e13..d699010 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -35,7 +35,6 @@
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -86,7 +85,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index c117a33..48b32dd 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -34,7 +34,6 @@
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -93,7 +92,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_PRIME "FEC0"
+#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
diff --git a/include/configs/netspace_v2.h b/include/configs/netspace_v2.h
index 82a1233..bb27ed7 100644
--- a/include/configs/netspace_v2.h
+++ b/include/configs/netspace_v2.h
@@ -60,11 +60,16 @@
*/
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+#define CONFIG_NR_DRAM_BANKS 1
+#ifdef CONFIG_INETSPACE_V2
+/* Different SDRAM configuration and size for Internet Space v2 */
+#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg)
+#endif
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
-#define CONFIG_NR_DRAM_BANKS 2
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
@@ -103,6 +108,17 @@
#define CONFIG_KIRKWOOD_GPIO
/*
+ * Enable I2C support
+ */
+#ifdef CONFIG_CMD_I2C
+/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
+#endif /* CONFIG_CMD_I2C */
+
+/*
* File systems support
*/
#define CONFIG_CMD_EXT2
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 7a76288..47ec39f 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -1,6 +1,8 @@
/*
- * (C) Copyright 2006-2008
- * Texas Instruments.
+ * Configuration settings for the TI OMAP3 EVM board.
+ *
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
* Author :
* Manikandan Pillai <mani.pillai@ti.com>
* Derived from Beagle Board and 3430 SDP code by
@@ -9,8 +11,6 @@
*
* Manikandan Pillai <mani.pillai@ti.com>
*
- * Configuration settings for the TI OMAP3 EVM board.
- *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -30,172 +30,82 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
-#define CONFIG_OMAP3_EVM 1 /* working with EVM */
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
+#ifndef __OMAP3EVM_CONFIG_H
+#define __OMAP3EVM_CONFIG_H
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
-/*
- * Display CPU and Board information
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
*/
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
+#include <config_cmd_default.h>
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-/*
- * Hardware drivers
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
*/
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
+/* Add auto-completion support */
+#define CONFIG_AUTO_COMPLETE
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_MMC 1
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
+/* ----------------------------------------------------------------------------
+ * Supported hardware
+ * ----------------------------------------------------------------------------
+ */
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR 1
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
/* USB
+ *
* Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
* Enable CONFIG_MUSB_UDD for Device functionalities.
*/
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_MUSB_HCD 1
-/* #define CONFIG_MUSB_UDC 1 */
-
-#ifdef CONFIG_USB_OMAP3
-
-#ifdef CONFIG_MUSB_HCD
-#define CONFIG_CMD_USB
-
-#define CONFIG_USB_STORAGE
-#define CONGIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
-
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_MUSB_HCD */
+#define CONFIG_USB_OMAP3
+#define CONFIG_MUSB_HCD
+/* #define CONFIG_MUSB_UDC */
-#ifdef CONFIG_MUSB_UDC
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "EVM"
-#endif /* CONFIG_MUSB_UDC */
-
-#endif /* CONFIG_USB_OMAP3 */
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMI /* iminfo */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
-
-/*
- * TWL4030
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
*/
-#define CONFIG_TWL4030_POWER 1
+#include "omap3_evm_common.h"
-/*
- * Board NAND Info.
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
*/
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access */
- /* nand at CS0 */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
-
-/* Environment information */
#define CONFIG_BOOTDELAY 10
-#define CONFIG_BOOTFILE "uImage"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
@@ -231,133 +141,4 @@
"fi; " \
"else run nandboot; fi"
-#define CONFIG_AUTO_COMPLETE 1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command */
- /* args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
- /* address */
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C 1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_ENV_IS_IN_ONENAND 1
-#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
-#endif
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
-
-/*
- * Support for relocation
- */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Define the board revision statically
- */
-/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
-
-/*----------------------------------------------------------------------------
- * SMSC9115 Ethernet from SMSC9118 family
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE 0x2C000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-/*
- * BOOTP fields
- */
-
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-
-#endif /* __CONFIG_H */
+#endif /* __OMAP3EVM_CONFIG_H */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
new file mode 100644
index 0000000..54aa7a7
--- /dev/null
+++ b/include/configs/omap3_evm_common.h
@@ -0,0 +1,292 @@
+/*
+ * Common configuration settings for the TI OMAP3 EVM board.
+ *
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __OMAP3_EVM_COMMON_H
+#define __OMAP3_EVM_COMMON_H
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_OMAP /* This is TI OMAP core */
+#define CONFIG_OMAP34XX /* belonging to 34XX family */
+#define CONFIG_OMAP3430 /* which is in a 3430 */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
+#define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */
+#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+
+/*
+ * Clock related definitions
+ */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* Size of environment - 128KB */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Size of malloc pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Stack sizes
+ * These values are used in start.S
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*
+ * Physical Memory Map
+ * Note 1: CS1 may or may not be populated
+ * Note 2: SDRAM size is expected to be at least 32MB
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20)
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C
+
+/* Limits for memtest */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/* -----------------------------------------------------------------------------
+ * Hardware drivers
+ * -----------------------------------------------------------------------------
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_OMAP34XX_I2C
+
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+
+/*
+ * PISMO support
+ */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+
+/* Monitor at start of flash - Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+/* Start location & size of environment */
+#define ONENAND_ENV_OFFSET 0x260000
+#define SMNAND_ENV_OFFSET 0x260000
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+
+/*
+ * NAND
+ */
+/* Physical address to access NAND */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE
+
+/* Physical address to access NAND at CS0 */
+#define CONFIG_SYS_NAND_BASE NAND_BASE
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* Timeout values (in ticks) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+
+#define CONFIG_SYS_JFFS2_MEM_NAND
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* Start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+/* Size of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE 0xf980000
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_OMAP3
+
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "EVM"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_OMAP3 */
+
+/* ----------------------------------------------------------------------------
+ * U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of Console IO buffer */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Size of print buffer */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of bootarg buffer */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_BOOTFILE "uImage"
+
+/*
+ * NAND / OneNAND
+ */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#endif
+
+#if !defined(CONFIG_ENV_IS_NOWHERE)
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_ENV_IS_IN_ONENAND
+#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
+#endif
+#endif /* CONFIG_ENV_IS_NOWHERE */
+
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+
+/* Ethernet (SMSC9115 from SMSC9118 family) */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
+
+/* BOOTP fields */
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+
+#endif /* CONFIG_CMD_NET */
+
+/* Support for relocation */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* -----------------------------------------------------------------------------
+ * Board specific
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Uncomment to define the board revision statically */
+/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
+
+#endif /* __OMAP3_EVM_COMMON_H */
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
new file mode 100644
index 0000000..691e4c2
--- /dev/null
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -0,0 +1,91 @@
+/*
+ * Configuration settings for quick boot from MMC on OMAP3 EVM.
+ *
+ * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ * Sanjeev Premi <premi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __OMAP3_EVM_QUICK_MMC_H
+#define __OMAP3_EVM_QUICK_MMC_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+
+/*
+ * Board revision is detected by probing the Ethernet chip.
+ *
+ * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
+ * this option can be removed. Generated binary is leaner by ~16Kbytes.
+ */
+#define CONFIG_CMD_NET
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* ----------------------------------------------------------------------------
+ * Supported hardware
+ * ----------------------------------------------------------------------------
+ */
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
+ */
+#include "omap3_evm_common.h"
+
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "silent=1"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc rescan 0; " \
+ "fatload mmc 0 0x82000000 uImage; " \
+ "bootm 0x82000000;"
+
+/*
+ * Update the bootargs as necessary e.g. size of memory, partition and fstype
+ */
+#define CONFIG_BOOTARGS \
+ "quiet " \
+ "console=ttyO0,115200n8 " \
+ "mem=128M " \
+ "noinitrd " \
+ "root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait"
+
+#endif /* __OMAP3_EVM_QUICK_MMC_H */
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
new file mode 100644
index 0000000..2d18314
--- /dev/null
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -0,0 +1,79 @@
+/*
+ * Configuration settings for quick boot from NAND on OMAP3 EVM.
+ *
+ * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ * Sanjeev Premi <premi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __OMAP3_EVM_QUICK_NAND_H
+#define __OMAP3_EVM_QUICK_NAND_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_CMD_NAND
+
+/*
+ * Board revision is detected by probing the Ethernet chip.
+ *
+ * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
+ * this option can be removed. Generated binary is leaner by ~16Kbytes.
+ */
+#define CONFIG_CMD_NET
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
+ */
+#include "omap3_evm_common.h"
+
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=no\0" \
+ "silent=1"
+
+#define CONFIG_BOOTCOMMAND \
+ "nandecc hw; " \
+ "nand read.i 0x80000000 280000 300000; " \
+ "bootm 0x80000000;"
+
+/*
+ * Update the bootargs as necessary e.g. size of memory, partition and fstype
+ */
+#define CONFIG_BOOTARGS \
+ "quiet " \
+ "console=ttyO0,115200n8 " \
+ "mem=128M " \
+ "noinitrd " \
+ "root=/dev/mtdblock4 rw " \
+ "rootfstype=jffs2 "
+
+#endif /* __OMAP3_EVM_QUICK_NAND_H */
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
new file mode 100644
index 0000000..a0252a2
--- /dev/null
+++ b/include/configs/omap3_mvblx.h
@@ -0,0 +1,313 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24@60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 889d5fc..380ef4f 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -165,4 +165,7 @@
#define COPY_BL2_SIZE 0x80000
#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
#endif /* __CONFIG_H */
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index e2c2eda..c068aa0 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -45,6 +45,13 @@
*/
#define CONFIG_SYS_TEXT_BASE 0x20002000
+/*
+ * since a number of boards are not being listed in linux
+ * arch/arm/tools/mach-types any more, the mach-types have to be
+ * defined here
+ */
+#define MACH_TYPE_OTC570 2166
+
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
diff --git a/include/configs/portl2.h b/include/configs/portl2.h
index a8543a5..e436cfe 100644
--- a/include/configs/portl2.h
+++ b/include/configs/portl2.h
@@ -46,7 +46,11 @@
#define CONFIG_PORTL2
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
-#define KM_ENV_BUS "pca9544a:70:a" /* I2C2 (Mux-Port 2)*/
+/*
+ * Note: This is only valid for HW > P1A if you got an outdated P1A
+ * use KM_ENV_BUS "pca9544a:70:a"
+ */
+#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/*
* portl2 has a fixed link to the XMPP backplane
diff --git a/include/configs/qong.h b/include/configs/qong.h
index c61a9b3..3346802 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -25,9 +25,9 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
-#define CONFIG_QONG 1
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_QONG
#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
#define CONFIG_MX31_CLK32 32768
@@ -36,14 +36,14 @@
#define CONFIG_SYS_TEXT_BASE 0xa0000000
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
/*
* Hardware drivers
@@ -58,7 +58,7 @@
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
#define CONFIG_PMIC
#define CONFIG_PMIC_SPI
@@ -71,14 +71,14 @@
/* FPGA */
#define CONFIG_FPGA
-#define CONFIG_QONG_FPGA 1
+#define CONFIG_QONG_FPGA
#define CONFIG_FPGA_BASE (CS1_BASE)
#define CONFIG_FPGA_LATTICE
#define CONFIG_FPGA_COUNT 1
#ifdef CONFIG_QONG_FPGA
/* Ethernet */
-#define CONFIG_DNET 1
+#define CONFIG_DNET
#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
/* Framebuffer and LCD */
@@ -92,6 +92,8 @@
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
/* USB */
#define CONFIG_CMD_USB
@@ -137,6 +139,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI
+#define CONFIG_CMD_UNZIP
#define CONFIG_BOARD_LATE_INIT
@@ -206,13 +209,13 @@
#define CONFIG_SYS_HZ 1000
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
-#define CONFIG_MISC_INIT_R 1
+#define CONFIG_MISC_INIT_R
/*-----------------------------------------------------------------------
* Stack sizes
*
@@ -262,7 +265,7 @@ extern int qong_nand_rdy(void *chip);
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
@@ -275,13 +278,13 @@ extern int qong_nand_rdy(void *chip);
* CFI FLASH driver setup
*/
/* Flash memory is CFI compliant */
-#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_SYS_FLASH_CFI
/* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_DRIVER
/* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* Use hardware sector protection */
-#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_PROTECTION
/*
* Filesystem
@@ -311,6 +314,6 @@ extern int qong_nand_rdy(void *chip);
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index a52b0a5..3434de7 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -220,6 +220,8 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX8998
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 4031016..cc14f97 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -243,4 +243,23 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#include <asm/arch/gpio.h>
+/*
+ * I2C Settings
+ */
+#define CONFIG_SOFT_I2C_GPIO_SCL s5pc210_gpio_part1_get_nr(b, 7)
+#define CONFIG_SOFT_I2C_GPIO_SDA s5pc210_gpio_part1_get_nr(b, 6)
+
+#define CONFIG_SOFT_I2C
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS 7
+
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX8998
+
#endif /* __CONFIG_H */
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 59c9fdb..fc8bb06 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -37,6 +37,9 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+/* Mach Type */
+#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
+
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
@@ -87,7 +90,10 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_MMC_U_BOOT
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR 0x00002488
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
new file mode 100644
index 0000000..6ef25cd
--- /dev/null
+++ b/include/configs/tt01.h
@@ -0,0 +1,254 @@
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * Configuration settings for the HALE TT-01 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136
+#define CONFIG_MX31
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+
+/*
+ * Physical Memory Map:
+ * CS settings are defined by i.MX31:
+ * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
+ * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
+ * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
+ *
+ * HALE set-up of the bluetechnix board for now is:
+ * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
+ * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
+ * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
+ * the flash chip is a mirrorbit S29WS256N !
+ * - the PSRAM is hooked to CS5 (0xB6000000)
+ * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
+ * - 64Mbit = 8MByte (will go away in the production set-up)
+ * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
+ * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
+ * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
+ *
+ * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
+ * is not used right now. We should be able to reduce the SOM to NAND flash
+ * only and boot from there.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
+/* default load address, 1MB up the road */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
+
+/* The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Size of malloc() pool, make sure possible frame buffer fits */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
+
+/* memtest works on all but the last 1MB (u-boot) and malloc area */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END \
+ (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
+
+/* CFI FLASH driver setup */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_SPANSION_S29WS_N
+/*
+ * TODO: Bluetechnix (the supplier of the SOM) did define these values
+ * in their original version of u-boot (1.2 or so). This should be
+ * reviewed.
+ *
+ * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ * #define CONFIG_SYS_FLASH_PROTECTION
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
+
+/*
+ * FLASH and environment organization, only the Spansion chip is supported:
+ * - it has 254 * 128kB + 8 * 32kB blocks
+ * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
+ * and 2 sectors with 128k as environment =
+ * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
+ * - this could be less, but this is only for developer versions of the board
+ * and no-one is going to use the NOR flash anyway.
+ *
+ * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
+ * way to large, but it avoids ENV overwrite (when updating u-boot) in case
+ * size breaks the next boundary (as it has with 128k).
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024) /* smaller for faster access */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Hardware drivers */
+
+/*
+ * on TT-01 UART1 pins are used by Audio, so we use UART2
+ * TT-01 implements a hardware that turns off components depending on
+ * the power level. In PL=1 the RS232 transceiver is usually off,
+ * make sure that the transceiver is enabled during PL=1 for testing!
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX31_UART2
+
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* MC13783 connected to CSPI3 and SS0 */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_SPI
+#define CONFIG_PMIC_FSL
+
+#define CONFIG_FSL_PMIC_BUS 2
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN 32
+
+#define CONFIG_RTC_MC13XXX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+/* console is UART2 on TT-01 */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/* ethernet setup for the onboard smc9118 */
+#define CONFIG_MII
+#define CONFIG_SMC911X
+/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
+#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
+#define CONFIG_SMC911X_16_BIT
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NAND
+/*
+ * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
+ * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
+ * a software locking scheme.
+ */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * currently a default setting for booting via script is implemented
+ * set user to login name and serverip to tftp host, define your
+ * boot behaviour in bootscript.loginname
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=dhcp bootscript.$(user); source\0"
+
+#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
+#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
+
+/* Miscellaneous configurable options */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "TT01> "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_NAND_MXC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+
+/*
+ * actually this is nothing someone wants to configure!
+ * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
+ * is not used by the driver.
+ */
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+
+/* the current u-boot driver does not use the nand flash setup! */
+#define CONFIG_SYS_NAND_LARGEPAGE
+/*
+ * it's not 16 bit:
+ * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ * the current u-boot mxc_nand.c tries to auto-detect, but this only
+ * reads the boot settings during reset (which might be wrong)
+ */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 8cb57ff..f77c546 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -34,6 +34,12 @@
/* NAND BOOT is the only boot method */
#define CONFIG_NAND_U_BOOT
+#ifndef MACH_TYPE_TX25
+#define MACH_TYPE_TX25 2177
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_TX25
+
#ifdef CONFIG_NAND_SPL
/* Start copying real U-boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index bee9e97..f321ad2 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -36,11 +36,13 @@
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOARD_LATE_INIT
+#ifndef MACH_TYPE_TTC_VISION2
+#define MACH_TYPE_TTC_VISION2 2775
+#endif
#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
/*
@@ -95,7 +97,7 @@
#define CONFIG_FSL_PMIC_CLK 2500000
#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13783
+#define CONFIG_RTC_MC13XXX
/*
* MMC Configs