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authorHan Xu <b45815@freescale.com>2015-10-09 13:29:41 -0500
committerHan Xu <b45815@freescale.com>2015-10-15 13:47:08 -0500
commit5281bf9f84ea586d6765ed8e8fe0302143eb2101 (patch)
treeff138a146ad4ecdd9624fbccf21d88807ed74a87 /include/configs
parent77e3c2ad2a08a5cfe9f055957c44590121658aeb (diff)
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MLK-11718-2: mtd: nand: change the BCH layout setting for large oob NAND
The cod change updated the NAND driver BCH ECC layout algorithm to support large oob size NAND chips(oob > 1024 bytes). Current implementation requires each chunk size larger than oob size so the bad block marker (BBM) can be guaranteed located in data chunk. The ECC layout always using the unbalanced layout(Ecc for both meta and Data0 chunk), but for the NAND chips with oob larger than 1k, the driver cannot support because BCH doesn’t support GF 15 for 2K chunk. The change keeps the data chunk no larger than 1k and adjust the ECC strength or ECC layout to locate the BBM in data chunk. General idea for large oob NAND chips is 1.Try all ECC strength from the minimum value required by NAND spec to the maximum one that works, any ECC makes the BBM locate in data chunk can be chosen. 2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, of course, we need to check if oob can afford it. Signed-off-by: Han Xu <b45815@freescale.com>
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