Merge git://www.denx.de/git/u-boot into uboot

31 files changed, 357 insertions, 134 deletions

diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index c14376e..0d644da 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -96,6 +96,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define PCI_SPEED		33333000        /* CPLD currenlty does not have PCI setup info */
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 4304ecc..7919991 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -37,6 +37,8 @@
 
 #define CONFIG_ETHER_ON_FEC1
 #define CONFIG_ETHER_ON_FEC2
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
 
 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
 #define CFG_DISCOVER_PHY
@@ -212,4 +214,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from flash	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index f12a3e6..9576fa5 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -38,6 +38,14 @@
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
 
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_VSC7385_ENET
+
+
 #ifdef CFG_66MHZ
 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
 #elif defined(CFG_33MHZ)
@@ -65,6 +73,22 @@
 #define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 
 /*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
@@ -214,19 +238,24 @@
 #define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
 #define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
 
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
+#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
+#define CFG_LBLAWBAR3_PRELIM	0xFA000000
+#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE	0xF0000000
 
-#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
 #define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
 #define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
 
-/* local bus read write buffer mapping */
-#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
-#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
-#define CFG_LBLAWBAR3_PRELIM	0xFA000000
-#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+#endif
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -263,13 +292,6 @@
 #define CFG_I2C_OFFSET		0x3000
 #define CFG_I2C2_OFFSET		0x3100
 
-/* TSEC */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
-#define CONFIG_NET_MULTI
-
 /*
  * General PCI
  * Addresses are mapped 1-1.
@@ -288,26 +310,31 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 
 /*
- * TSEC configuration
+ * TSEC
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI		1
-#endif
-
-#define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_TSEC1		1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII			/* MII PHY management */
 
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_TSEC2		1
+#define CFG_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHYIDX		0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#define TSEC1_PHY_ADDR			0x1c
-#define TSEC2_PHY_ADDR			4
-#define TSEC1_FLAGS			TSEC_GIGABIT
-#define TSEC2_FLAGS			TSEC_GIGABIT
-#define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
+#define CFG_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHYIDX		0
+#endif
+
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC1"
@@ -496,10 +523,13 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:E0:0C:00:95:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
+#endif
+
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
+#endif
 
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index ff7101f..af78726 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -299,7 +299,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index bf5ef4b..94c4c6b 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -66,6 +66,13 @@
 #define CFG_IMMR		0xE0000000
 
 /*
+ * System performance
+ */
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CFG_SPCR_OPT		1	/* (0-1) Optimize transactions between  CSB and the SEC and QUICC Engine block */
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
@@ -82,17 +89,51 @@
 /* Manually set up DDR parameters
  */
 #define CFG_DDR_SIZE		64	/* MB */
-#define CFG_DDR_CS0_CONFIG	0x80840101
-#define CFG_DDR_TIMING_0	0x00220802
-#define CFG_DDR_TIMING_1	0x3935d322
-#define CFG_DDR_TIMING_2	0x0f9048ca
+#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
+				| CSCONFIG_ODT_WR_ACS \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
+				/* 0x80010101 */
+#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x00220802 */
+#define CFG_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x26253222 */
+#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| (31 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x1f9048c7 */
 #define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
-#define CFG_DDR_MODE		0x44400232
+#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/* 0x02000000 */
+#define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44480232 */
 #define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x03200064
+#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03200064 */
 #define CFG_DDR_CS0_BNDS	0x00000003
-#define CFG_DDR_SDRAM_CFG	0x43080000
+#define CFG_DDR_SDRAM_CFG	( SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE )
+				/* 0x43080000 */
 #define CFG_DDR_SDRAM_CFG2	0x00401000
 #endif
 
@@ -280,10 +321,10 @@
 #define CFG_I2C_OFFSET	0x3000
 
 /*
- * Config on-board RTC
+ * Config on-board EEPROM
  */
-#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+#define CFG_I2C_EEPROM_ADDR     0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
 
 /*
  * General PCI
@@ -376,6 +417,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ASKENV
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f32c4f7..be2ab45 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -346,7 +346,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000	/* 1M */
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 48c2736..6b8b74d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -68,12 +68,16 @@
 
 #define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
 
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
 
-/* On-board devices */
+/*
+ * On-board devices
+ */
 
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
-#define CONFIG_VSC7385		/* The Vitesse 7385 5-port switch */
+#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
 #endif
 
 #define CONFIG_PCI
@@ -88,9 +92,6 @@
 /* I2C */
 #ifdef CONFIG_HARD_I2C
 
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
@@ -155,7 +156,7 @@
 #define CFG_MEMTEST_END		0x2000
 
 #define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
-				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
@@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_FLASH_SIZE		16		/* FLASH size in MB */
 #define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
 
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
 /*
  * BRx, ORx, LBLAWBARx, and LBLAWARx
  */
@@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* Vitesse 7385 */
 
-#ifdef CONFIG_VSC7385
-
 #define CFG_VSC7385_BASE	0xF8000000
 
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
 #define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
@@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET	0x25000
-#define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
+
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_PHYIDX		0
 #define TSEC2_FLAGS		TSEC_GIGABIT
@@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_TSEC1
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:E0:0C:00:8C:01
 #endif
 
-#ifdef CONFIG_TSEC2
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index c8dcbc6..46451c4 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -194,6 +194,7 @@
 #define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
 #define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
@@ -374,7 +375,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 27b037a..a4f6af6 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -30,8 +30,8 @@
  * System Clock Setup
  */
 #ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_83XX_CLKIN		33000000
-#define CONFIG_SYS_CLK_FREQ		33000000
+#define CONFIG_83XX_CLKIN		33333333
+#define CONFIG_SYS_CLK_FREQ		33333333
 #define PCI_33M				1
 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_10X1
 #else
@@ -89,8 +89,8 @@
 
 #define CFG_83XX_DDR_USES_CS0
 
-#undef CONFIG_DDR_ECC		/* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+#define CONFIG_DDR_ECC		/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
 
 /*
  * DDRCDR - DDR Control Driver Register
@@ -104,20 +104,44 @@
  */
 #define CONFIG_DDR_II
 #define CFG_DDR_SIZE		256 /* MB */
-#define CFG_DDRCDR		0x80080001
 #define CFG_DDR_CS0_BNDS	0x0000000f
 #define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
-				 CSCONFIG_COL_BIT_10)
-#define CFG_DDR_TIMING_0	0x00330903
-#define CFG_DDR_TIMING_1	0x3835a322
-#define CFG_DDR_TIMING_2	0x00104909
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
+				 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
+#define CFG_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CFG_DDR_SDRAM_CFG2	0x00001000
+#define CFG_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CFG_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 #define CFG_DDR_MODE		0x47800432
 #define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x045b0100
-#define CFG_DDR_SDRAM_CFG	0x03000000
-#define CFG_DDR_SDRAM_CFG2	0x00001000
+
+#define CFG_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CFG_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
+				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (10 << TIMING_CFG1_REFREC_SHIFT) | \
+				 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CFG_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (0 << TIMING_CFG2_CPO_SHIFT))
+
+#define CFG_DDR_TIMING_3	0x00000000
 
 /*
  * Memory test
@@ -184,6 +208,11 @@
  * NAND flash on the local bus
  */
 #define CFG_NAND_BASE		0x60000000
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_UPM	1
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
 #define CFG_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */
@@ -230,6 +259,7 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
@@ -290,7 +320,7 @@
 #define CFG_UEC1_TX_CLK		QE_CLK9
 #define CFG_UEC1_ETH_TYPE	GIGA_ETH
 #define CFG_UEC1_PHY_ADDR	2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -301,7 +331,7 @@
 #define CFG_UEC2_TX_CLK		QE_CLK4
 #define CFG_UEC2_ETH_TYPE	GIGA_ETH
 #define CFG_UEC2_PHY_ADDR	4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 /*
@@ -340,6 +370,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
@@ -499,27 +530,44 @@
    "consoledev=ttyS0\0"\
    "loadaddr=a00000\0"\
    "fdtaddr=900000\0"\
-   "bootfile=uImage\0"\
    "fdtfile=dtb\0"\
    "fsfile=fs\0"\
    "ubootfile=u-boot.bin\0"\
+   "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
    "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
    		"$mtdparts panic=1\0"\
    "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
    "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
    		"$gatewayip:$netmask:$hostname:$netdev:off "\
    		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
+   "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
+		"rootfstype=jffs2 rw\0"\
    "tftp_get_uboot=tftp 100000 $ubootfile\0"\
    "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
    "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
    "tftp_get_fs=tftp c00000 $fsfile\0"\
+   "nand_erase_kernel=nand erase 0 400000\0"\
+   "nand_erase_dtb=nand erase 400000 20000\0"\
+   "nand_erase_fs=nand erase 420000 3be0000\0"\
+   "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
+   "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
+   "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
+   "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
+   "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
    "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
    		"cp.b 100000 ff800000 $filesize\0"\
+   "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
+		"nand_write_kernel\0"\
+   "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
+   "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
+   "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
+		"nand_reflash_fs\0"\
    "boot_m=bootm $loadaddr - $fdtaddr\0"\
-   "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
-   		"boot_m\0"\
+   "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
    "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
-   		"boot_m\0"\
+		"boot_m\0"\
+   "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
+		"boot_m\0"\
    ""
 
 #define CONFIG_BOOTCOMMAND "run dhcpboot"
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 5586533..b307bf7 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -338,7 +338,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1964946..90812e9 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -32,6 +32,15 @@
 
 #define CONFIG_PCI	1
 
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
+#define CONFIG_VSC7385_ENET
+
 /*
  * System Clock Setup
  */
@@ -118,6 +127,22 @@
 #define CFG_IMMR		0xE0000000
 
 /*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
@@ -251,15 +276,38 @@
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CFG_BR1_PRELIM		(CFG_NAND_BASE | \
+				 (2 << BR_DECC_SHIFT) |	/* Use HW ECC */ \
+				 BR_PS_8 |		/* Port Size = 8 bit */ \
+				 BR_MS_FCM |		/* MSEL = FCM */ \
+				 BR_V)			/* valid */
+#define CFG_OR1_PRELIM		(0xFFFF8000 |		/* length 32K */ \
+				 OR_FCM_CSCT | \
+				 OR_FCM_CST | \
+				 OR_FCM_CHT | \
+				 OR_FCM_SCY_1 | \
+				 OR_FCM_TRLX | \
+				 OR_FCM_EHTR)
+#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE	0xF0000000
 
-/* VSC7385 Gigabit Switch support */
-#define CONFIG_VSC7385_ENET
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM		0xf0000801		/* Base address */
 #define CFG_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE	/* Access Base */
 #define CFG_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
 
+#endif
+
 /*
  * Serial Port
  */
@@ -276,6 +324,11 @@
 #define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
 #define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
 
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
 #ifdef	CFG_HUSH_PARSER
@@ -285,6 +338,7 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
@@ -312,7 +366,7 @@
 #define CFG_PCI_MMIO_BASE	0x90000000
 #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_BASE		0x00000000
 #define CFG_PCI_IO_PHYS		0xE0300000
 #define CFG_PCI_IO_SIZE		0x100000 /* 1M */
 
@@ -324,43 +378,43 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
-#undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI	1
-#endif
-
 /*
  * TSEC
  */
-#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#ifdef CONFIG_TSEC_ENET
 
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_TSEC1			1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII			/* MII PHY management */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME		"TSEC0"
-#define CONFIG_TSEC2			1
-#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CFG_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			2
-#define TSEC2_PHY_ADDR			0x1c
 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
+#endif
 
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CFG_TSEC2_OFFSET		0x25000
+#define TSEC2_PHY_ADDR			0x1c
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHYIDX			0
+#endif
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC0"
 
+#endif
+
 /*
  * Environment
  */
@@ -529,10 +583,15 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
-#define CONFIG_ETHADDR	00:04:9f:ef:04:01
-#define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
-#define CONFIG_ETH1ADDR	00:04:9f:ef:04:02
+#ifdef CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR		00:04:9f:ef:04:01
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:04:9f:ef:04:02
+#endif
+
+#define CONFIG_HAS_FSL_DR_USB
 
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5ea7b25..85934d7 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -100,6 +100,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 174215c..77eea73 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -83,6 +83,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR 	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 7334088..3f3f741 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -49,6 +49,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -82,6 +85,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 /*
@@ -273,6 +277,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM   0xf8000801
 #define CFG_OR3_PRELIM   0xfff00ff7
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index a894209..c83d9e2 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -98,6 +98,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a3db9f4..fc8ad88 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -57,6 +57,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -96,6 +99,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
@@ -296,6 +300,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM	 0xf8000801
 #define CFG_OR3_PRELIM	 0xfff00ff7
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 93877ae..500b57c 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -49,6 +49,9 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
+#define CONFIG_FSL_VIA
+#define CONFIG_FSL_CDS_EEPROM
+
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
  * assume this is the AMD flash associated with the CDS board.
@@ -82,6 +85,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 /*
@@ -273,6 +277,8 @@ extern unsigned long get_clock_freq(void);
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
+#define CONFIG_FSL_CADMUS
+
 #define CADMUS_BASE_ADDR 0xf8000000
 #define CFG_BR3_PRELIM   0xf8000801
 #define CFG_OR3_PRELIM   0xfff00ff7
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 08884b3..e30302c 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -95,6 +95,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index a12d193..7bb20e5 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -90,6 +90,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 819bee7..bd058fc 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -92,6 +92,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 8902f42..38a26dc 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -94,6 +94,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 2bbfe9a..946b3c2 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -99,6 +99,7 @@
 #else
   #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 9a0e9b8..b36c826 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -252,12 +252,22 @@
 	"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
 #endif
 
+#if defined(CONFIG_TQM5200_B)
+#define ENV_FLASH_LAYOUT						\
+	"fdt_addr=FC100000\0"						\
+	"kernel_addr=FC140000\0"					\
+	"ramdisk_addr=FC600000\0"
+#else	/* !CONFIG_TQM5200_B */
+#define ENV_FLASH_LAYOUT						\
+	"fdt_addr=FC0A0000\0"						\
+	"kernel_addr=FC0C0000\0"					\
+	"ramdisk_addr=FC300000\0"
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"console=ttyPSC0\0"						\
-	"fdt_addr=FC0A0000\0"						\
-	"kernel_addr=FC0C0000\0"					\
-	"ramdisk_addr=FC300000\0"					\
+	ENV_FLASH_LAYOUT						\
 	"kernel_addr_r=400000\0"					\
 	"fdt_addr_r=600000\0"						\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
@@ -400,8 +410,9 @@
 # if defined(CONFIG_TQM5200_B)
 #  if defined(CFG_LOWBOOT)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:1m(firmware),"	\
-						"1536k(kernel),"	\
-						"3584k(small-fs),"	\
+						"256k(dtb),"		\
+						"2304k(kernel),"	\
+						"2560k(small-fs),"	\
 						"2m(initrd),"		\
 						"8m(misc),"		\
 						"16m(big-fs)"
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 21e8baf..fca5f74 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -89,6 +89,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
 #define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 /*
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 893924b..ba6d932 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -27,6 +27,12 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 516203a..49a7234 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -87,6 +87,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define CFG_PCI1_ADDR	(CFG_CCSRBAR+0x8000)
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index f9ede5f..81a1e07 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -93,6 +93,7 @@
 #else
   #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
 #endif
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 8491d97..4df461d 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -81,8 +81,8 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_IDE
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_EEPROM
 
@@ -173,37 +173,14 @@
 #define PCNET_HAS_PROM         1
 
 /************************************************************
- * IDE/ATA stuff
- ************************************************************/
-#define CFG_IDE_MAXBUS		1   /* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
-/*#define CFG_ATA_IDE1_OFFSET	0x0170	/###* ide1 offset */
-#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
-#define CFG_ATA_REG_OFFSET	0	/* reg offset */
-#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
-#define CFG_ATA_BASE_ADDR       0
-
-#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
-#undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
-#undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
-
-/************************************************************
 *SATA/Native Stuff
 ************************************************************/
-#define CFG_SATA_SUPPORTED      1
 #define CFG_SATA_MAXBUS         2       /*Max Sata buses supported */
 #define CFG_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
-#define CFG_SATA_MAXDEVICES     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CFG_SATA_MAX_DEVICE     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
 #define CFG_ATA_PIIX            1       /*Supports ata_piix driver */
 
 /************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI			/* enable ATAPI Support */
-
-/************************************************************
  * DISK Partition support
  ************************************************************/
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 047e1cf..fc5d0cc 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -114,6 +114,7 @@
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
 #endif
 #define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index e09dd71..15f690a 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -127,6 +127,7 @@
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
 #endif
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index b035857..f12765d 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -594,7 +594,5 @@ typedef unsigned int led_id_t;
 
 #define OF_CPU			"PowerPC,MPC870@0"
 #define OF_TBCLK		(MPC8XX_HZ / 16)
-#define CONFIG_OF_HAS_BD_T	1
-#define CONFIG_OF_HAS_UBOOT_ENV	1
 
 #endif	/* __CONFIG_H */