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| author | Ye.Li <B37916@freescale.com> | 2015-03-02 12:02:31 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2015-03-02 12:02:31 +0800 |
| commit | 58fd869e3097b7461fbfae3d94e3ebbd30ae2474 (patch) | |
| tree | 970266a5c19803876bac0532b4a4ec216a68fa82 /include/configs | |
| parent | 3554b7d45db7b9bb18ef4e28244becdc06db2bfc (diff) | |
| download | u-boot-imx-58fd869e3097b7461fbfae3d94e3ebbd30ae2474.zip u-boot-imx-58fd869e3097b7461fbfae3d94e3ebbd30ae2474.tar.gz u-boot-imx-58fd869e3097b7461fbfae3d94e3ebbd30ae2474.tar.bz2 | |
MLK-10351 imx: mx7d: Add 19x19 DDR3L ARM2 board support
Add BSP codes, configuration head file and build target for
19x19 DDR3L ARM2 board with basic functions:
ENET2, I2C, SD/eMMC/MMC, USB, QSPI, ECSPI, pfuze3000 PMIC.
Build target: mx7d_19x19_ddr3_arm2_config
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/mx7d_19x19_ddr3_arm2.h | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/include/configs/mx7d_19x19_ddr3_arm2.h b/include/configs/mx7d_19x19_ddr3_arm2.h new file mode 100644 index 0000000..c096df6 --- /dev/null +++ b/include/configs/mx7d_19x19_ddr3_arm2.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 19x19 DDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_19X19_DDR3_ARM2_CONFIG_H +#define __MX7D_19X19_DDR3_ARM2_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define PHYS_SDRAM_SIZE SZ_1G + + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#define CONFIG_FEC_DMA_MINALIGN 64 + +/* ENET2 */ +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR + +#ifdef CONFIG_SYS_BOOT_QSPI +#define CONFIG_SYS_USE_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_SPINOR +#define CONFIG_SYS_USE_SPINOR +#define CONFIG_ENV_IS_IN_SPI_FLASH +#else +#define CONFIG_SYS_USE_QSPI /* Enable the QSPI flash at default */ +#define CONFIG_ENV_IS_IN_MMC +#endif + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +/* PMIC */ +#define CONFIG_PFUZE3000_PMIC_I2C +#ifdef CONFIG_PFUZE3000_PMIC_I2C +#define CONFIG_PMIC_I2C_BUS 0 +#define CONFIG_PMIC_I2C_SLAVE 0x8 +#endif +#endif + +#ifdef CONFIG_SYS_USE_SPINOR +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(4, 19)<<8)) +#endif + +#define CONFIG_VIDEO + +#include "mx7d_arm2.h" + +#endif |