Merge branch 'master' of git://git.denx.de/u-boot

59 files changed, 1252 insertions, 58 deletions

diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
index 3f2f614..38b962f 100644
--- a/include/configs/Alaska8220.h
+++ b/include/configs/Alaska8220.h
@@ -31,6 +31,8 @@
 #define CONFIG_MPC8220		1
 #define CONFIG_ALASKA8220	1	/* ... on Alaska board	*/
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
 #define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 706c13e..b7574bf 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -61,6 +61,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot		    */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported		    */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 48e29a2..89edbde 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -61,6 +61,8 @@
 
 #undef	CONFIG_ECC			/* enable ECC support */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* which initialization functions to call for this board */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOARD_PRE_INIT
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index f85cff7..3a347ea 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -37,6 +37,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 610151f..d547681 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -469,6 +469,8 @@
 
 #define CFG_HID2 HID2_HBE
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* DDR @ 0x00000000 */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10)
 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index e0a887c..7a5d0aa 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -453,6 +453,7 @@
 /*
  * MMU Setup
  */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 32f57ac..977c041 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -468,6 +468,7 @@
 /*
  * MMU Setup
  */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 1276a12..9ca2a2b 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -483,6 +483,8 @@
  * MMU Setup
  */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* DDR: cache cacheable */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 119e7ac..bd77540 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -626,6 +626,7 @@
 
 
 #define CFG_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR @ 0x00000000 */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index c72de03..38410a1 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -555,6 +555,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_HID0_FINAL	CFG_HID0_INIT
 
 #define CFG_HID2	HID2_HBE
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR  */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 983575e..fcfbe6f 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -515,6 +515,8 @@
  * MMU Setup
  */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* DDR: cache cacheable */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 7b7d6f5..adedcb9 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -419,6 +419,8 @@
  * MMU Setup
  */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* DDR: cache cacheable */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index e92493a..4e159a0 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -502,6 +502,7 @@
 /*
  * MMU Setup
  */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
 #define CFG_SDRAM_LOWER		CFG_SDRAM_BASE
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index f7e6fd2..29c2490 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -524,6 +524,8 @@
  * MMU Setup
  */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* DDR: cache cacheable */
 #define CFG_SDRAM_LOWER		CFG_SDRAM_BASE
 #define CFG_SDRAM_UPPER		(CFG_SDRAM_BASE + 0x10000000)
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 15ff0ea..a051b6d 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -55,6 +55,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported & enabled */
 #define CONFIG_ALTIVEC		1
 
 /*
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 9acc3da..49ee7ff 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -67,6 +67,7 @@
 #define BANK_INTERLEAVING		0x22000000
 #define SUPER_BANK_INTERLEAVING		0x23000000
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
 
 #define CONFIG_ALTIVEC		1
 
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 6eb6444..259178f 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -40,6 +40,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 6cb3022..d21783b 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -42,6 +42,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 71fa36b..4c44735 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -50,6 +50,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index bff2edf..bfb478a 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -47,6 +47,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index a86939e..89fc465 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -423,6 +423,8 @@ extern int tqm834x_num_flash_banks;
 #define CFG_HID0_FINAL	CFG_HID0_INIT
 #define CFG_HID2	HID2_HBE
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* DDR 0 - 512M */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 31f10dd..598fe7b 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -48,6 +48,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
index 00c4ff0..1b4195a 100644
--- a/include/configs/Yukon8220.h
+++ b/include/configs/Yukon8220.h
@@ -31,6 +31,8 @@
 #define CONFIG_MPC8220		1
 #define CONFIG_YUKON8220	1	/* ... on Yukon board	*/
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
 #define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index c975a24..4226529 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -372,6 +372,8 @@
 #define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 #define CFG_HID2	HID2_HBE
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Internal Definitions
  *
diff --git a/include/configs/aev.h b/include/configs/aev.h
index e3f810c..c5e4759 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -41,6 +41,8 @@
 #define CONFIG_AEVFIFO		1
 #define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index c891fa8..342ce2a 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -28,6 +28,7 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
+#define AT91_CPU_NAME		"AT91CAP9"
 #define AT91_MAIN_CLOCK		200000000	/* from 12 MHz crystal */
 #define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
 #define CFG_HZ			1000000		/* 1us resolution */
@@ -55,11 +56,19 @@
 #undef CONFIG_USART2
 #define CONFIG_USART3		1	/* USART 3 is DBGU */
 
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
-				"root=/dev/mtdblock1 rw rootfstype=jffs2"
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CFG_CONSOLE_IS_IN_ENV		1
 
-/* #define CONFIG_ENV_OVERWRITE	1 */
+#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
@@ -94,9 +103,9 @@
 #define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
 #define CFG_MAX_DATAFLASH_BANKS		1
 #define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
-#define AT91_SPI_CLK			20000000
-#define DATAFLASH_TCSS			(0xFA << 16)
-#define DATAFLASH_TCHS			(0x8 << 24)
+#define AT91_SPI_CLK			15000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
 
 /* NOR flash */
 #define CFG_FLASH_CFI			1
@@ -110,6 +119,7 @@
 #define NAND_MAX_CHIPS			1
 #define CFG_MAX_NAND_DEVICE		1
 #define CFG_NAND_BASE			0x40000000
+#define CFG_NAND_DBW_8			1
 
 /* Ethernet */
 #define CONFIG_MACB			1
@@ -143,7 +153,12 @@
 #define CFG_ENV_OFFSET		0x4200
 #define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
 #define CFG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC003DE00 0x72000000 0x200040; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x72000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock1 "			\
+				"mtdparts=physmap-flash.0:-(nor);"	\
+				"at91_nand:-(root) "			\
+				"rw rootfstype=jffs2"
 
 #else
 
@@ -154,6 +169,12 @@
 #define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_ENV_OFFSET)
 #define CFG_ENV_SIZE		0x4000
 #define CONFIG_BOOTCOMMAND	"cp.b 0x10040000 0x72000000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock4 "			\
+				"mtdparts=physmap-flash.0:16k(bootstrap)ro,"\
+				"16k(env),224k(uboot)ro,-(linux);"	\
+				"at91_nand:-(root) "			\
+				"rw rootfstype=jffs2"
 
 #endif
 
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 41c418f..675224e 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -56,10 +56,6 @@
 #define CONFIG_USART3		1	/* USART 3 is DBGU */
 
 #define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
-				"root=/dev/mtdblock0 rw rootfstype=jffs2"
-
-/* #define CONFIG_ENV_OVERWRITE	1 */
 
 /*
  * BOOTP options
@@ -96,7 +92,7 @@
 #define CFG_MAX_DATAFLASH_BANKS		2
 #define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define CFG_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
-#define AT91_SPI_CLK			33000000
+#define AT91_SPI_CLK			15000000
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
@@ -104,6 +100,7 @@
 #define NAND_MAX_CHIPS			1
 #define CFG_MAX_NAND_DEVICE		1
 #define CFG_NAND_BASE			0x40000000
+#define CFG_NAND_DBW_8			1
 
 /* NOR flash - no real flash on this board */
 #define CFG_NO_FLASH			1
@@ -142,7 +139,11 @@
 #define CFG_ENV_OFFSET		0x4200
 #define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
 #define CFG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC003DE00 0x22000000 0x200040; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=at91_nand:-(root) "		\
+				"rw rootfstype=jffs2"
 
 #elif CFG_USE_DATAFLASH_CS1
 
@@ -152,7 +153,11 @@
 #define CFG_ENV_OFFSET		0x4200
 #define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
 #define CFG_ENV_SIZE		0x4200
-#define CONFIG_BOOTCOMMAND	"cp.b 0xD003DE00 0x22000000 0x200040; bootm"
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=at91_nand:-(root) "		\
+				"rw rootfstype=jffs2"
 
 #else /* CFG_USE_NANDFLASH */
 
@@ -162,6 +167,12 @@
 #define CFG_ENV_OFFSET_REDUND	0x80000
 #define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock5 "			\
+				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
+				"256k(uboot)ro,128k(env1)ro,"		\
+				"128k(env2)ro,2M(linux),-(root) "	\
+				"rw rootfstype=jffs2"
 
 #endif
 
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
new file mode 100644
index 0000000..e53a23f
--- /dev/null
+++ b/include/configs/at91sam9261ek.h
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9261EK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME		"AT91SAM9261"
+#define AT91_MAIN_CLOCK		198656000	/* from 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK	99328000	/* peripheral = main / 2 */
+#define CFG_HZ			1000000		/* 1us resolution */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#define CONFIG_AT91SAM9261	1	/* It's an Atmel AT91SAM9261 SoC*/
+#define CONFIG_AT91SAM9261EK	1	/* on an AT91SAM9261EK Board	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART	1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CFG_CONSOLE_IS_IN_ENV		1
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x20000000
+#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH		1
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS		2
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
+#define AT91_SPI_CLK			15000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* NAND flash */
+#define NAND_MAX_CHIPS			1
+#define CFG_MAX_NAND_DEVICE		1
+#define CFG_NAND_BASE			0x40000000
+#define CFG_NAND_DBW_8			1
+
+/* NOR flash - no real flash on this board */
+#define CFG_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x30000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT		1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW		1
+#define LITTLEENDIAN			1
+#define CONFIG_DOS_PARTITION		1
+#define CFG_USB_OHCI_CPU_INIT		1
+#define CFG_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
+#define CFG_USB_OHCI_SLOT_NAME		"at91sam9261"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+
+#define CFG_LOAD_ADDR			0x22000000	/* load address */
+
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			0x23e00000
+
+#define CFG_USE_DATAFLASH_CS0		1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH	1
+#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET		0x4200
+#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=at91_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x60000
+#define CFG_ENV_OFFSET_REDUND	0x80000
+#define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock5 "			\
+				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
+				"256k(uboot)ro,128k(env1)ro,"		\
+				"128k(env2)ro,2M(linux),-(root) "	\
+				"rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"U-Boot> "
+#define CFG_CBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
new file mode 100644
index 0000000..a8194b5
--- /dev/null
+++ b/include/configs/at91sam9263ek.h
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9263EK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME		"AT91SAM9263"
+#define AT91_MAIN_CLOCK		199919000	/* from 16.367 MHz crystal */
+#define AT91_MASTER_CLOCK	99959500	/* peripheral = main / 2 */
+#define CFG_HZ			1000000		/* 1us resolution */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#define CONFIG_AT91SAM9263	1	/* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_AT91SAM9263EK	1	/* on an AT91SAM9263EK Board	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART	1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CFG_CONSOLE_IS_IN_ENV		1
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x20000000
+#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH		1
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS		1
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK			15000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* NOR flash, if populated */
+#if 1
+#define CFG_NO_FLASH			1
+#else
+#define CFG_FLASH_CFI			1
+#define CFG_FLASH_CFI_DRIVER		1
+#define PHYS_FLASH_1			0x10000000
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_MAX_FLASH_SECT		256
+#define CFG_MAX_FLASH_BANKS		1
+#endif
+
+/* NAND flash */
+#define NAND_MAX_CHIPS			1
+#define CFG_MAX_NAND_DEVICE		1
+#define CFG_NAND_BASE			0x40000000
+#define CFG_NAND_DBW_8			1
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_MULTI		1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW		1
+#define LITTLEENDIAN			1
+#define CONFIG_DOS_PARTITION		1
+#define CFG_USB_OHCI_CPU_INIT		1
+#define CFG_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CFG_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+
+#define CFG_LOAD_ADDR			0x22000000	/* load address */
+
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			0x23e00000
+
+#define CFG_USE_DATAFLASH		1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH	1
+#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET		0x4200
+#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				"mtdparts=at91_nand:-(root) "\
+				"rw rootfstype=jffs2"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x60000
+#define CFG_ENV_OFFSET_REDUND	0x80000
+#define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock5 " \
+				"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
+				"rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"U-Boot> "
+#define CFG_CBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
new file mode 100644
index 0000000..2ad8d05
--- /dev/null
+++ b/include/configs/at91sam9rlek.h
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9RLEK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME		"AT91SAM9RL"
+#define AT91_MAIN_CLOCK		200000000	/* from 12.000 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
+#define CFG_HZ			1000000		/* 1us resolution */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#define CONFIG_AT91SAM9RL	1	/* It's an Atmel AT91SAM9RL SoC*/
+#define CONFIG_AT91SAM9RLEK	1	/* on an AT91SAM9RLEK Board	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART	1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CFG_WHITE_ON_BLACK		1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_RGB565		1
+#define CFG_CONSOLE_IS_IN_ENV		1
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_USB
+
+#define CONFIG_CMD_NAND		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x20000000
+#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH		1
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS		1
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK			15000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* NOR flash - not present */
+#define CFG_NO_FLASH			1
+
+/* NAND flash */
+#define NAND_MAX_CHIPS			1
+#define CFG_MAX_NAND_DEVICE		1
+#define CFG_NAND_BASE			0x40000000
+#define CFG_NAND_DBW_8			1
+
+/* Ethernet - not present */
+
+/* USB - not supported */
+
+#define CFG_LOAD_ADDR			0x22000000	/* load address */
+
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			0x23e00000
+
+#define CFG_USE_DATAFLASH		1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH	1
+#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET		0x4200
+#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				"mtdparts=at91_nand:-(root) "\
+				"rw rootfstype=jffs2"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x60000
+#define CFG_ENV_OFFSET_REDUND	0x80000
+#define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock5 " \
+				"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
+				"rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"U-Boot> "
+#define CFG_CBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 5aad043..3fc9975 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7000		1
@@ -112,8 +114,11 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
 
 #define CONFIG_ATMEL_USART		1
 #define CONFIG_MACB			1
@@ -137,11 +142,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
-#define CFG_SDRAM_16BIT			1
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -150,27 +153,20 @@
 #define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
 
 #define CFG_MALLOC_LEN			(256*1024)
-#define CFG_MALLOC_END							\
-	({								\
-		DECLARE_GLOBAL_DATA_PTR;				\
-		CFG_SDRAM_BASE + gd->sdram_size;			\
-	})
-#define CFG_MALLOC_START		(CFG_MALLOC_END - CFG_MALLOC_LEN)
-
 #define CFG_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
 #define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)
 
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 95aeab6..ba18eb6 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7000		1
@@ -139,9 +141,9 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_REGINFO
 
 #undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
 #undef CONFIG_CMD_XIMG
 
@@ -170,10 +172,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -185,17 +186,17 @@
 #define CFG_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
-#define CFG_MAXARGS			8
+#define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index 194788b..a528ddf 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7001		1
@@ -153,10 +155,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -167,17 +168,17 @@
 #define CFG_MALLOC_LEN			(256*1024)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
 #define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index b81fc21..fc9585e 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7002		1
@@ -153,11 +155,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
-#define CFG_SDRAM_16BIT			1
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -168,17 +168,17 @@
 #define CFG_MALLOC_LEN			(256*1024)
 
 /* Allow 2MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00200000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT			"Uboot> "
+#define CFG_PROMPT			"U-Boot> "
 #define CFG_CBSIZE			256
 #define CFG_MAXARGS			16
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
new file mode 100644
index 0000000..9fd49a5
--- /dev/null
+++ b/include/configs/atstk1006.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/memory-map.h>
+
+#define CONFIG_AVR32			1
+#define CONFIG_AT32AP			1
+#define CONFIG_AT32AP7000		1
+#define CONFIG_ATSTK1006		1
+#define CONFIG_ATSTK1000		1
+
+#define CONFIG_ATSTK1000_EXT_FLASH	1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ				1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL			1
+#define CFG_POWER_MANAGER		1
+#define CFG_OSC0_HZ			20000000
+#define CFG_PLL0_DIV			1
+#define CFG_PLL0_MUL			7
+#define CFG_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
+#define CFG_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
+#define CFG_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
+#define CFG_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
+#define CFG_CLKDIV_PBB			1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT			0x04
+
+#undef CONFIG_USART0
+#define CONFIG_USART1			1
+#undef CONFIG_USART2
+#undef CONFIG_USART3
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=mtd3 fbmem=2400k"
+
+#define CONFIG_BOOTCOMMAND						\
+	"fsload; bootm $(fileaddr)"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT			1
+#define CONFIG_AUTOBOOT_KEYED		1
+#define CONFIG_AUTOBOOT_PROMPT				\
+	"Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+#define CONFIG_NET_MULTI		1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART		1
+#define CONFIG_MACB			1
+#define CONFIG_PIO2			1
+#define CFG_NR_PIOS			5
+#define CFG_HSDRAMC			1
+#define CONFIG_MMC			1
+
+#define CFG_DCACHE_LINESZ		32
+#define CFG_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI			1
+#define CFG_FLASH_CFI_DRIVER		1
+#endif
+
+#define CFG_FLASH_BASE			0x00000000
+#define CFG_FLASH_SIZE			0x800000
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		135
+
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_SIZE			65536
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN			(256*1024)
+#define CFG_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT			"U-Boot> "
+#define CFG_CBSIZE			256
+#define CFG_MAXARGS			16
+#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP			1
+
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
+#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x3f00000)
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 0f7bb61..f097e2c 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -40,6 +40,8 @@
 
 #define CONFIG_BOARD_EARLY_INIT_R
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index d554348..ef50c7c 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -31,6 +31,8 @@
 #define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
 #define CONFIG_CM5200		1	/* ... on CM5200 platform */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Supported commands
  */
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index 1b30e51..fffd1fe 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -50,6 +50,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported 	  */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index e5a8897..ad7cf76 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -40,6 +40,8 @@
 
 #define CONFIG_BOARD_EARLY_INIT_R
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 4281d73..ec4ed1e 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -65,7 +65,8 @@
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
-#define CONFIG_MXC_SPI_IFACE	1
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
 
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index c89f041..6ec92c3 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -40,6 +40,8 @@
 
 #define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 980e9fe..c985927 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -41,6 +41,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index a9c86f9..e4c3f72 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -40,6 +40,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
 /*
  * Serial console configuration
  *
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 5218d9c..8dfb9aa 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -50,6 +50,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 1503598..b6843af 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -35,6 +35,7 @@
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
 #define CONFIG_MOTIONPRO	1	/* ... on Promess Motion-PRO board */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /*
  * BOOTP options
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index f614e67..a218f75 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -39,7 +39,7 @@
 #define CONFIG_MPC7448HPC2
 
 #define CONFIG_74xx
-#define CONFIG_750FX		/* this option to enable init of extended BATs */
+#define CONFIG_HIGH_BATS	/* High BATs supported */
 #define CONFIG_ALTIVEC		/* undef to disable */
 
 #define CFG_BOARD_NAME		"MPC7448 HPC II"
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 38b27bb..e0046ec 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -35,6 +35,7 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 #define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /*
  * Command line configuration.
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 2ea48a6..37ba872 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -62,7 +62,8 @@
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
-#define CONFIG_MXC_SPI_IFACE	1	/* Default SPI interface number */
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
 
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 8dde1ef..88bdb03 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -37,6 +37,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 0dac516..0913b14 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -42,6 +42,7 @@
 
 #if defined (CONFIG_P3M750)
 #define CONFIG_750FX			/* 750GL/GX/FX			*/
+#define CONFIG_HIGH_BATS		/* High BATs supported		*/
 #define CFG_BOARD_NAME		"P3M750"
 #define CFG_BUS_HZ		100000000
 #define CFG_BUS_CLK		CFG_BUS_HZ
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index 2ce39c9..c065d33 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -49,6 +49,7 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
 /*
  * Serial console configuration
  */
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
new file mode 100644
index 0000000..622a5d4
--- /dev/null
+++ b/include/configs/quad100hd.h
@@ -0,0 +1,298 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * quad100hd.h - configuration for Quad100hd board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_QUAD100HD	1		/* Board is Quad100hd	*/
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_405EP		1		/* Specifc 405EP support*/
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+
+#define PLLMR0_DEFAULT		PLLMR0_266_133_66 /* no PCI */
+#define PLLMR1_DEFAULT		PLLMR1_266_133_66 /* no PCI */
+
+/* the environment is in the EEPROM by default */
+#define CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_FLASH
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
+#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET	1
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_LOG
+#undef CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0  1
+#define CFG_SDRAM_SIZE      0x02000000      /* 32 MB */
+
+/* FIX! SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL            3       /* CAS latency */
+#define CFG_SDRAM_tRP           20      /* PRECHARGE command period */
+#define CFG_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
+#define CFG_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
+#define CFG_SDRAM_tRFC          66      /* Auto refresh period */
+
+/*
+ * JFFS2
+ */
+#define CFG_JFFS2_FIRST_BANK    0
+#ifdef  CFG_KERNEL_IN_JFFS2
+#define CFG_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
+#else /* kernel not in JFFS */
+#define CFG_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
+#endif
+#define CFG_JFFS2_NUM_BANKS     1
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CFG_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CFG_BASE_BAUD		691200
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN	2		/* bytes of address */
+
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 8 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CFG_EEPROM_SIZE			0x2000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFC00000
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(TEXT_BASE)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define	CFG_FLASH_CFI_DRIVER
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_INCREMENT      0       /* there is only one bank         */
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+/* the environment is located before u-boot */
+#define CFG_ENV_ADDR		(TEXT_BASE - CFG_ENV_SECT_SIZE)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SECT_SIZE)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x400		/* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x00000000
+#define CFG_ENABLE_CRC_16	1       /* Intrinsyc formatting used crc16 */
+#endif
+
+/* partly from PPCBoot */
+/* NAND */
+#define CONFIG_NAND
+#ifdef CONFIG_NAND
+#define CFG_NAND_BASE   0x60000000
+#define CFG_NAND_CS	10   /* our CS is GPIO10 */
+#define CFG_NAND_RDY	23   /* our RDY is GPIO23 */
+#define CFG_NAND_CE	24   /* our CE is GPIO24  */
+#define CFG_NAND_CLE	31   /* our CLE is GPIO31 */
+#define CFG_NAND_ALE	30   /* our ALE is GPIO30 */
+#define NAND_MAX_CHIPS	1
+#define CFG_MAX_NAND_DEVICE	1
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+/* see ./cpu/ppc4xx/start.S */
+#define CFG_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of OCM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ * Taken from PPCBoot board/icecube/icecube.h
+ */
+
+/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+#define CFG_EBC_PB0AP		0x04002480
+/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
+#define CFG_EBC_PB0CR		0xFFC5A000
+#define CFG_EBC_PB1AP           0x04005480
+#define CFG_EBC_PB1CR           0x60018000
+#define CFG_EBC_PB2AP           0x00000000
+#define CFG_EBC_PB2CR           0x00000000
+#define CFG_EBC_PB3AP           0x00000000
+#define CFG_EBC_PB3CR           0x00000000
+#define CFG_EBC_PB4AP           0x00000000
+#define CFG_EBC_PB4CR           0x00000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * Taken in part from PPCBoot board/icecube/icecube.h
+ */
+/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+#define CFG_GPIO0_OSRH		0x55555550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xFFFF8097
+#define CFG_GPIO0_ODR		0x00000000
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_IPADDR		192.168.1.67
+#define CONFIG_SERVERIP		192.168.1.50
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_LOADADDR		300000
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 0ebc674..7481556 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -570,6 +570,8 @@
 
 #define CFG_HID2 HID2_HBE
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* DDR @ 0x00000000 */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index 4578cae..3e47eb8 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -42,6 +42,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 23ed87f..6dc9eff 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -227,7 +227,8 @@
  */
 #define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
 
-
+/* PCI is clocked by the external source at 33 MHz */
+#define CONFIG_PCI_CLK_FREQ	33000000
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index c62b977..18f5533 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -31,6 +31,8 @@
 #define CONFIG_MPC8220		1
 #define CONFIG_SORCERY		1	/* Sorcery board */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
 #define CFG_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 49213dc..69d2d67 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -44,6 +44,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index dc1d7e1..042750e 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -40,6 +40,8 @@
 
 #define CONFIG_BOARD_EARLY_INIT_R
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported 			*/
+
 /*
  * Serial console configuration
  */
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index e24d6f7..c203522 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -46,6 +46,8 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot */
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Serial console configuration
  */