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authorChander Kashyap <chander.kashyap@linaro.org>2012-02-05 23:01:45 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-02-12 10:11:30 +0100
commit5e46f83cc3569b95cef68dfd0722663260af91d0 (patch)
treee034f53d74bd747554fcbb311515665b19c93a93 /include/configs
parent8aca4d6436dda130a4711940bd10a0a9220b0eb1 (diff)
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Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/s5pc210_universal.h1
-rw-r--r--include/configs/trats.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index be000cb..8286680 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -49,6 +49,7 @@
/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 24000000
+#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/trats.h b/include/configs/trats.h
index acb3241..10f11d9 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -49,6 +49,7 @@
/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 24000000
+#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG