ColdFire: Modules header files cleanup

Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

8 files changed, 49 insertions, 81 deletions

diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index 876ec20..a13db7c 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -178,7 +178,7 @@
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE1
 #define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE1
 
-#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 #define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
 #define CONFIG_SYS_INT_FLASH_ENABLE	0x21
 
@@ -218,17 +218,13 @@
  * Memory bank definitions
  */
 
-#define CONFIG_SYS_CS0_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		2*1024*1024
-#define CONFIG_SYS_CS0_WIDTH		16
-#define CONFIG_SYS_CS0_RO		0
-#define CONFIG_SYS_CS0_WS		6
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
 
 #define CONFIG_SYS_CS3_BASE		0xE0000000
-#define CONFIG_SYS_CS3_SIZE		1*1024*1024
-#define CONFIG_SYS_CS3_WIDTH		16
-#define CONFIG_SYS_CS3_RO		0
-#define CONFIG_SYS_CS3_WS		6
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS3_MASK		0x000F0001
 
 /*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index e6c87ef..8c66f87 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -215,7 +215,7 @@
 #	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 #endif
 
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -251,13 +251,13 @@
  * CS7 - Available
  */
 #ifdef NORFLASH_PS32BIT
-#	define CONFIG_SYS_CS0_BASE	0xFFC0
+#	define CONFIG_SYS_CS0_BASE	0xFFC00000
 #	define CONFIG_SYS_CS0_MASK	0x003f0001
-#	define CONFIG_SYS_CS0_CTRL	0x1D00
+#	define CONFIG_SYS_CS0_CTRL	0x00001D00
 #else
-#	define CONFIG_SYS_CS0_BASE	0xFFE0
+#	define CONFIG_SYS_CS0_BASE	0xFFE00000
 #	define CONFIG_SYS_CS0_MASK	0x001f0001
-#	define CONFIG_SYS_CS0_CTRL	0x1D80
+#	define CONFIG_SYS_CS0_CTRL	0x00001D80
 #endif
 
 #endif				/* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 8699ef9..e3830e5 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -125,7 +125,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 
 #if 0 /* test-only */
 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -170,15 +170,15 @@
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CSAR0		0xffe0
-#define	CONFIG_SYS_CSCR0		0x1980		/* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CSMR0		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CSAR1		0xe000
-#define	CONFIG_SYS_CSCR1		0x0d80		/* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CSMR1		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 3a5c12f..378e45a 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -90,7 +90,7 @@
 
 #define CONFIG_DRIVER_DM9000
 #ifdef CONFIG_DRIVER_DM9000
-#	define CONFIG_DM9000_BASE	((CONFIG_SYS_CSAR1 << 16) | 0x300)
+#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
 #	define DM9000_IO		CONFIG_DM9000_BASE
 #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
 #	undef CONFIG_DM9000_DEBUG
@@ -202,7 +202,7 @@
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	1000
@@ -233,21 +233,13 @@
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
-#define CONFIG_SYS_CSAR0		0xFF80
-#define CONFIG_SYS_CSMR0		0x007F0021
-#define CONFIG_SYS_CSCR0		0x1D80
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		0x007F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
 
-#define CONFIG_SYS_CSAR1               0xE000
-#define CONFIG_SYS_CSMR1               0x00000001
-#define CONFIG_SYS_CSCR1               0x3DD8
-
-#define CONFIG_SYS_CSAR2		0
-#define CONFIG_SYS_CSMR2		0
-#define CONFIG_SYS_CSCR2		0
-
-#define CONFIG_SYS_CSAR3		0
-#define CONFIG_SYS_CSMR3		0
-#define CONFIG_SYS_CSCR3		0
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		0x00000001
+#define CONFIG_SYS_CS1_CTRL		0x00003DD8
 
 /*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index c2cd62b..86de97d 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -166,7 +166,7 @@
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	1000
@@ -182,21 +182,9 @@
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
-#define CONFIG_SYS_CSAR0		0xFFE0
-#define CONFIG_SYS_CSMR0		0x001F0021
-#define CONFIG_SYS_CSCR0		0x1D80
-
-#define CONFIG_SYS_CSAR1		0
-#define CONFIG_SYS_CSMR1		0
-#define CONFIG_SYS_CSCR1		0
-
-#define CONFIG_SYS_CSAR2		0
-#define CONFIG_SYS_CSMR2		0
-#define CONFIG_SYS_CSCR2		0
-
-#define CONFIG_SYS_CSAR3		0
-#define CONFIG_SYS_CSMR3		0
-#define CONFIG_SYS_CSCR3		0
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_MASK		0x001F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
 
 /*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 1f3539e..db48d76 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -173,7 +173,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 #ifdef CONFIG_MONITOR_IS_IN_RAM
 #define CONFIG_SYS_MONITOR_BASE	0x20000
@@ -211,13 +211,13 @@
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_AR0_PRELIM		(CONFIG_SYS_FLASH_BASE >> 16)
-#define CONFIG_SYS_CR0_PRELIM		0x1980
-#define CONFIG_SYS_MR0_PRELIM		0x001F0001
+#define CONFIG_SYS_CS0_BASE		0xffe00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
 
-#define CONFIG_SYS_AR1_PRELIM		0x3000
-#define CONFIG_SYS_CR1_PRELIM		0x1900
-#define CONFIG_SYS_MR1_PRELIM		0x00070001
+#define CONFIG_SYS_CS1_BASE		0x30000000
+#define CONFIG_SYS_CS1_CTRL		0x00001900
+#define CONFIG_SYS_CS1_MASK		0x00070001
 
 /*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index a8a2655..15590cf 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -165,7 +165,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 #define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
 #define CONFIG_SYS_INT_FLASH_ENABLE	0x21
 
@@ -212,18 +212,10 @@
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_CS0_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		2*1024*1024
-#define CONFIG_SYS_CS0_WIDTH		16
-#define CONFIG_SYS_CS0_RO		0
-#define CONFIG_SYS_CS0_WS		6
-/*
-#define CONFIG_SYS_CS3_BASE		0xE0000000
-#define CONFIG_SYS_CS3_SIZE		1*1024*1024
-#define CONFIG_SYS_CS3_WIDTH		16
-#define CONFIG_SYS_CS3_RO		0
-#define CONFIG_SYS_CS3_WS		6
-*/
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
+
 /*-----------------------------------------------------------------------
  * Port configuration
  */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 18ffbfd..25f3a26 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -206,7 +206,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffc00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
 #if 0 /* test-only */
 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -257,15 +257,15 @@
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CSAR0               0xffc0
-#define	CONFIG_SYS_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffc00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CSAR1               0xe000
-#define	CONFIG_SYS_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration