Merge branch 'master' into next

59 files changed, 1516 insertions, 574 deletions

diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 1b74526..7ee05e5 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -67,7 +67,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 #define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 1a2bc1c..89ba139 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -196,9 +196,9 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(TEXT_BASE) + 1)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index e231fa7..d0b4d11 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -216,6 +216,8 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 2319c58..69c8c6e 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -92,6 +92,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
 
@@ -212,6 +213,8 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index bbdc211..8e82aac 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -193,7 +193,6 @@
 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
 #define CONFIG_SYS_OR1_PRELIM		0xFFFFE8F0		/* length 32K */
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index f633f24..14cbc45 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -266,7 +266,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index fff888ab..532c3df 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -70,7 +70,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
@@ -99,7 +98,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
@@ -231,8 +230,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 79a52d9..f22b752 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -79,7 +79,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
@@ -258,7 +257,6 @@
 #define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
 #define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 46a141a..5ac1916 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -62,7 +62,6 @@
 /* below can be toggled for performance analysis. otherwise use default */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #undef  CONFIG_BTB			    /* toggle branch predition */
-#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
 #define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
 
@@ -161,7 +160,6 @@
 #define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
 #define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 7ada8a2..399189c 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -63,7 +63,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #define CONFIG_BTB			    /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
@@ -281,7 +280,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index cdbbea6..9b1b34c 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -66,7 +66,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
@@ -97,7 +96,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
@@ -207,8 +206,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK      1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END       0x00004000      /* End of used area in RAM */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 083afba..e1bd45e 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -69,7 +69,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 #define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
@@ -100,7 +99,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
@@ -303,7 +302,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR3_PRELIM	 0xf8000801
 #define CONFIG_SYS_OR3_PRELIM	 0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index f9419cc..c92f82d 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -63,7 +63,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
 #define CONFIG_BTB			    /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
 
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
@@ -279,7 +278,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index f67d489..bf4bd2c 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -73,7 +73,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
 
@@ -254,7 +253,6 @@
 #define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
 #define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ab3e6d6..da1f454 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -61,7 +61,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
 #define CONFIG_BTB				/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING			/* toggle addr streaming   */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
@@ -92,7 +91,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
@@ -265,7 +264,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR5_PRELIM	 0xf8010801
 #define CONFIG_SYS_OR5_PRELIM	 0xffff69f7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index c3693b8..6c7a364 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -71,7 +71,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
@@ -93,12 +92,14 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
+#define CONFIG_SYS_DDR_TLB_START 9
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
@@ -114,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
+#define CONFIG_SYS_DDR_MODE_1		0x00440462
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400000
 
 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
@@ -248,8 +249,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 					| PIXIS_VCFGEN1_TSEC3SER \
 					| PIXIS_VCFGEN1_TSEC4SER)
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index f2fe4a6..4bd3e0b 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -81,6 +81,9 @@
 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
@@ -206,7 +209,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
@@ -271,11 +273,13 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x0000000
 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 /* For RTL8139 */
@@ -283,18 +287,18 @@
 #define _IO_BASE		0x00000000
 
 /* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
 
 /* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
 
@@ -362,7 +366,7 @@
 
 #define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
@@ -373,7 +377,7 @@
 
 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
@@ -388,6 +392,17 @@
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
 /*
  * BAT4		32M	Cache-inhibited, guarded
  * 0xe200_0000	1M	PCI-Express 2 I/O
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 69b4c44..5a83296 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS	(CONFIG_SYS_FLASH_BASE \
 					 | CONFIG_SYS_PHYS_ADDR_HIGH)
 
-
 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 
-/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
-#define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
-					 ((x & 0x300000000ULL) >> 19)))
-#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
-#endif
-
 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 				 | 0x00001001)	/* port size 16bit */
 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
@@ -268,7 +259,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index bc2d825..4ecf806 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -130,7 +130,6 @@
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 #undef	CONFIG_SYS_RAMBOOT
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index a147aff..34de947 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -799,7 +799,7 @@ typedef unsigned int led_id_t;
 #define CONFIG_CDP_DEVICE_ID_PREFIX	"NP"	/* netphone */
 #define CONFIG_CDP_PORT_ID		"eth%d"
 #define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_VERSION		"u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
 #define CONFIG_CDP_PLATFORM		"Intracom NetPhone"
 #define CONFIG_CDP_TRIGGER		0x20020001
 #define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 63810b3..004b3c8 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -775,7 +775,7 @@
 #define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta */
 #define CONFIG_CDP_PORT_ID		"eth%d"
 #define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot 1.0" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_VERSION		"u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
 #define CONFIG_CDP_PLATFORM		"Intracom NetTA"
 #define CONFIG_CDP_TRIGGER		0x20020001
 #define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index 61c5547..70995fa 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -750,7 +750,7 @@ typedef unsigned int led_id_t;
 #define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta2 */
 #define CONFIG_CDP_PORT_ID		"eth%d"
 #define CONFIG_CDP_CAPABILITIES		0x00000010
-#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_VERSION		"u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
 #define CONFIG_CDP_PLATFORM		"Intracom NetTA2"
 #define CONFIG_CDP_TRIGGER		0x20020001
 #define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 0393366..d0a37d7 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -60,39 +60,24 @@
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
@@ -102,7 +87,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
@@ -166,15 +150,9 @@
 #define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
 
-#if 0 /* test-only */
-#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-#else
 #define CONFIG_SYS_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
 #define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
-#endif
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -215,22 +193,10 @@
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
-
-#else /* Use EEPROM for environment variables */
-
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
 				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
 
 #define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
 #define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
@@ -327,14 +293,6 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#if 0 /* test-only */
-#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#else
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 #define CONFIG_SYS_TEMP_STACK_OCM	  1
 /* On Chip Memory location */
@@ -346,7 +304,6 @@
 #define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#endif
 
 /*
  * Internal Definitions
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index c3a7f81..41e290d 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -71,7 +71,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
@@ -161,7 +160,6 @@
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index b3bcf23..6b4e2dd 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -72,7 +72,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
@@ -164,7 +163,6 @@
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 7219bb8..f9f1002 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -219,8 +219,8 @@
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
 #endif
-#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
-					/* 440EPx errata CHIP 11	*/
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes */
+						  /* 440EPx errata CHIP 11 */
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -490,8 +490,8 @@
 #endif
 
 /* Memory Bank 1 (RESET) initialization */
-#define CFG_EBC_PB1AP		0x7f817200 //0x03017200
-#define CFG_EBC_PB1CR		(CFG_RESET_BASE | 0x1c000)
+#define CONFIG_SYS_EBC_PB1AP		0x7f817200 /* 0x03017200 */
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_RESET_BASE | 0x1c000)
 
 /* Memory Bank 4 (FPGA / 32Bit) initialization */
 #define CONFIG_SYS_EBC_PB4AP		0x03840f40	/* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 48c9339..3419631 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -75,7 +75,6 @@
 /* below can be toggled for performance analysis. otherwise use default */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
 #undef	CONFIG_BTB			    /* toggle branch predition	*/
-#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
@@ -186,7 +185,6 @@
 #define CONFIG_SYS_BCSR		((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 2961a1b..796030d 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -171,7 +171,6 @@ extern int tqm834x_num_flash_banks;
 #undef  CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 2d4048a..6d205a7 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -106,7 +106,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache		*/
 #define CONFIG_BTB			/* toggle branch predition	*/
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/
 
 #define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
 
@@ -234,7 +233,6 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x20000000	/* LB refresh timer presc.*/
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_CCSRBAR \
 				 + 0x04010000)	/* Initial RAM address	*/
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
new file mode 100644
index 0000000..1df6855
--- /dev/null
+++ b/include/configs/XPEDITE5200.h
@@ -0,0 +1,546 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5200 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548		1
+#define CONFIG_XPEDITE5200	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5200"
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR + 0x8000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
+ * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY	25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 BR_PS_8		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
+				 OR_GPCM_BCTLD		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_4		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 BR_PS_8		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_END		0x4000
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11			1
+#define CONFIG_SYS_I2C_RTC_ADDR			0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR		2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
+#define CONFIG_SYS_PCA953X_FLASH_WP		0x20
+#define CONFIG_SYS_PCA953X_MONARCH		0x40
+#define CONFIG_SYS_PCA953X_EREADY		0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0		0x01
+#define CONFIG_SYS_PCA953X_P14_IO1		0x02
+#define CONFIG_SYS_PCA953X_P14_IO2		0x04
+#define CONFIG_SYS_PCA953X_P14_IO3		0x08
+#define CONFIG_SYS_PCA953X_P14_IO4		0x10
+#define CONFIG_SYS_PCA953X_P14_IO5		0x20
+#define CONFIG_SYS_PCA953X_P14_IO6		0x40
+#define CONFIG_SYS_PCA953X_P14_IO7		0x80
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+#define TSEC4_FLAGS		TSEC_GIGABIT
+#define TSEC4_PHY_ADDR		4
+#define TSEC4_PHYIDX		0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff     Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff     Sec FDT (256KB)
+ * faf00000 - fbefffff     Sec OS image (16MB)
+ * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	MK_STR(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	MK_STR(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/uImage-XPedite5200\0"			\
+	"fdtfile=/home/user/xpedite5200.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
new file mode 100644
index 0000000..3bc0fe8
--- /dev/null
+++ b/include/configs/XPEDITE5370.h
@@ -0,0 +1,589 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5370 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8572		1
+#define CONFIG_XPEDITE5370	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5370"
+#define CONFIG_NUM_CPUS		2	/* 2 Cores */
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
+#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR + 0xa000)
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR + 0x9000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_XACS		| \
+				 OR_GPCM_ACS_DIV2	| \
+				 OR_GPCM_SCY_8		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR		| \
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
+				 OR_FCM_PGS	| \
+				 OR_FCM_CSCT	| \
+				 OR_FCM_CST	| \
+				 OR_FCM_CHT	| \
+				 OR_FCM_SCY_1	| \
+				 OR_FCM_TRLX	| \
+				 OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_END		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_DS1621_ADDR	0x48
+#define CONFIG_DTT_DS1621
+#define CONFIG_DTT_SENSORS		{ 0 }
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO/EEPROM/SRAM */
+#define CONFIG_DS4510
+#define CONFIG_SYS_I2C_DS4510_ADDR	0x51
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
+#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
+#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - VPX P1 */
+#define CONFIG_SYS_PCIE1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+/* PCIE2 - PEX8518 */
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_ETHPRIME		"eTSEC2"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DS4510
+#define CONFIG_CMD_DS4510_INFO
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff     Sec FDT (256KB)
+ * f6f00000 - f7efffff     Sec OS image (16MB)
+ * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	MK_STR(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	MK_STR(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/uImage-XPedite5370\0"			\
+	"fdtfile=/home/user/xpedite5370.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 755952f..d63a1a0 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -29,6 +29,7 @@
 /* ARM asynchronous clock */
 #define AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
 #define AT91_MASTER_CLOCK	89999598	/* peripheral = main / 2 */
+#define CONFIG_SYS_AT91_PLLB	0x107c3e18	/* PLLB settings for USB */
 #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
@@ -149,7 +150,7 @@
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CFG_LONGHELP		1
+#define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
@@ -166,4 +167,3 @@
 #endif
 
 #endif
-
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 6e9f5e5..7ce8205 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -235,18 +235,15 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
 #define CONFIG_CMD_FPGA
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
+#undef CONFIG_CMD_NFS
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index d71ed44..dff47fc 100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -53,6 +53,9 @@
 #define CONFIG_SYS_USE_NOR		1
 #endif
 
+/* uncommnet if you want to use UBI */
+#define CONFIG_SYS_USE_UBI
+
 #include <asm/arch/omap2420.h>	/* get chip and board defs */
 
 #define	V_SCLK	12000000
@@ -73,8 +76,9 @@
  * Size of malloc() pool
  */
 #define	CONFIG_ENV_SIZE SZ_128K	/* Total Size of Environment Sector */
-#define	CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_128K)
-#define	CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define	CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_1M)
+/* bytes reserved for initial data */
+#define	CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
@@ -116,6 +120,13 @@
 #define	CONFIG_CMD_DIAG
 #define	CONFIG_CMD_ONENAND
 
+#ifdef CONFIG_SYS_USE_UBI
+#define	CONFIG_CMD_JFFS2
+#define	CONFIG_CMD_UBI
+#define	CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#endif
+
 #undef	CONFIG_CMD_AUTOSCRIPT
 
 #ifndef	CONFIG_SYS_USE_NOR
@@ -133,24 +144,39 @@
 #define	CONFIG_BOOTFILE	"uImage"
 #define	CONFIG_ETHADDR	00:0E:99:00:24:20
 
-#ifdef	CONFIG_APOLLON_PLUS
-# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#ifdef CONFIG_APOLLON_PLUS
+#define CONFIG_SYS_MEM	"mem=64M"
+#else
+#define CONFIG_SYS_MEM	"mem=128"
+#endif
+
+#ifdef CONFIG_SYS_USE_UBI
+#define CONFIG_SYS_UBI "ubi.mtd=4"
 #else
-# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#define CONFIG_SYS_UBI ""
 #endif
 
+#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
+	" console=ttyS0,115200n8" \
+	" ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
+	"apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
+	CONFIG_SYS_UBI
+
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"Image=tftp 0x80008000 Image; go 0x80008000\0"			\
 	"zImage=tftp 0x80180000 zImage; go 0x80180000\0"		\
 	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0"		\
 	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0"		\
-	"xloader=tftp 0x80180000 x-load.bin; cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"	\
+	"xloader=tftp 0x80180000 x-load.bin; "				\
+	" cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"		\
 	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0"	\
 	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0"	\
 	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0"	\
-	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\
+	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
 	"onesyncboot=run syncmode oneboot\0"				\
-	"updateb=tftp 0x80180000 u-boot-onenand.bin; onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0"					\
+	"updateb=tftp 0x80180000 u-boot-onenand.bin; "			\
+	" onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
+	"ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
 	"bootcmd=run uboot\0"
 
 /*
@@ -164,14 +190,15 @@
 /* Print Buffer Size */
 #define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define	CONFIG_SYS_MAXARGS	16	/* max number of command args */
-#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define	CONFIG_SYS_MEMTEST_START	(OMAP2420_SDRC_CS0)	/* memtest works on */
+/* Boot Argument Buffer Size */
+#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_START	(OMAP2420_SDRC_CS0)
 #define	CONFIG_SYS_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)
 
 #undef	CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */
-
-#define	CONFIG_SYS_LOAD_ADDR	(OMAP2420_SDRC_CS0)	/* default load address */
+/* default load address */
+#define	CONFIG_SYS_LOAD_ADDR	(OMAP2420_SDRC_CS0)
 
 /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
  * or by 32KHz clk, or from external sig. This rate is divided by a local
@@ -211,13 +238,15 @@
 # define	CONFIG_SYS_MAX_FLASH_BANKS	1
 # define	CONFIG_SYS_MAX_FLASH_SECT	1024
 /*-----------------------------------------------------------------------
-
  * CFI FLASH driver setup
  */
-# define	CONFIG_SYS_FLASH_CFI	1	/* Flash memory is CFI compliant */
+/* Flash memory is CFI compliant */
+# define	CONFIG_SYS_FLASH_CFI	1
 # define	CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
-# define	CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w sector protection*/
+/* Use buffered writes (~10x faster) */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
+/* Use h/w sector protection*/
+# define	CONFIG_SYS_FLASH_PROTECTION	1
 
 #else	/* !CONFIG_SYS_USE_NOR */
 # define	CONFIG_SYS_NO_FLASH	1
@@ -228,4 +257,15 @@
 #define	CONFIG_ENV_IS_IN_ONENAND	1
 #define CONFIG_ENV_ADDR		0x00020000
 
+#ifdef CONFIG_SYS_USE_UBI
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"onenand0=onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(bootloader),"	\
+					"128k(params),"			\
+					"2m(kernel),"			\
+					"16m(rootfs),"			\
+					"32m(fs),"			\
+					"-(ubifs)"
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index 30a7cb4..b2baf1b 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -29,9 +29,11 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91CAP9"
-#define AT91_MAIN_CLOCK		200000000	/* from 12 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
-#define CONFIG_SYS_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_AT91_PLLB	0x10073e01	/* PLLB settings for USB */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -136,6 +138,8 @@
 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00700000	/* AT91_BASE_UHP */
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91cap9"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
 #define CONFIG_SYS_LOAD_ADDR			0x72000000	/* load address */
 
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 633a053..c7e83cc 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -1,7 +1,7 @@
 /*
  * Rick Bronson <rick@efn.org>
  *
- * Configuation settings for the AT91RM9200DK board.
+ * Configuration settings for the AT91RM9200DK board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -45,33 +45,35 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  * Size of malloc() pool
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index be9a8eb..1538929 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -28,9 +28,12 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		198656000	/* from 18.432 MHz crystal */
-#define AT91_MASTER_CLOCK	99328000	/* peripheral = main / 2 */
-#define CONFIG_SYS_HZ			1000000		/* 1us resolution */
+#define AT91_CPU_NAME		"AT91SAM9260"
+#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_AT91_PLLB	0x107c3e18	/* PLLB settings for USB */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -121,16 +124,13 @@
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#undef CONFIG_SYS_USE_DATAFLASH_CS0
-#define CONFIG_SYS_USE_DATAFLASH_CS1		1
-#undef CONFIG_SYS_USE_NANDFLASH
-
 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index add31c9..0016b4f 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -29,9 +29,10 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9261"
-#define AT91_MAIN_CLOCK		198656000	/* from 18.432 MHz crystal */
-#define AT91_MASTER_CLOCK	99328000	/* peripheral = main / 2 */
-#define CONFIG_SYS_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -136,21 +137,19 @@
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#define CONFIG_SYS_USE_DATAFLASH_CS0		1
-#undef CONFIG_SYS_USE_NANDFLASH
-
 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 #define CONFIG_ENV_IS_IN_DATAFLASH	1
 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
-#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_OFFSET	0x4200
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_SIZE		0x4200
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
@@ -159,6 +158,20 @@
 				"mtdparts=at91_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
+#elif CONFIG_SYS_USE_DATAFLASH_CS3
+
+/* bootstrap + u-boot + env + linux in dataflash on CS3 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=at91_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
 #else /* CONFIG_SYS_USE_NANDFLASH */
 
 /* bootstrap + u-boot + env + linux in nandflash */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 555cb7f..d9ebc87 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -29,9 +29,11 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9263"
-#define AT91_MAIN_CLOCK		199919000	/* from 16.367 MHz crystal */
-#define AT91_MASTER_CLOCK	99959500	/* peripheral = main / 2 */
-#define CONFIG_SYS_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		16367660	/* 16.367 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_AT91_PLLB	0x133a3e8d	/* PLLB settings for USB */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -142,15 +144,13 @@
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#define CONFIG_SYS_USE_DATAFLASH		1
-#undef CONFIG_SYS_USE_NANDFLASH
-
 #ifdef CONFIG_SYS_USE_DATAFLASH
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 648d60e..35fefc4 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -29,9 +29,10 @@
 
 /* ARM asynchronous clock */
 #define AT91_CPU_NAME		"AT91SAM9RL"
-#define AT91_MAIN_CLOCK		200000000	/* from 12.000 MHz crystal */
-#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
-#define CONFIG_SYS_HZ			1000000		/* 1us resolution */
+#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral */
+#define AT91_CPU_CLOCK		200000000	/* cpu */
+#define CONFIG_SYS_HZ		1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
@@ -117,9 +118,6 @@
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			0x23e00000
 
-#define CONFIG_SYS_USE_DATAFLASH		1
-#undef CONFIG_SYS_USE_NANDFLASH
-
 #ifdef CONFIG_SYS_USE_DATAFLASH
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index f8e8801..faf6304 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -102,7 +102,7 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |	\
 					 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 
-#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 16k		*/
+#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k		*/
 #define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k		*/
 #define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
 
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 527921e..d9acb47 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -44,33 +44,35 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
-#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x3399c1d4 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 38fd25c..2df77cf 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -45,33 +45,35 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */
-#define PLLBR_VAL	0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x21914159 /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x21914159 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  * Size of malloc() pool
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 58694cc..ea6cf0d 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -53,6 +53,13 @@
 #define CONFIG_HOSTNAME		katmai
 #include "amcc-common.h"
 
+/*
+ * For booting 256K-paged Linux we should have 16MB of memory
+ * for Linux initial memory map
+ */
+#undef CONFIG_SYS_BOOTMAPSZ
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 
@@ -189,6 +196,7 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 55cda32..1ce8c69 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -51,6 +51,8 @@
 #define CONFIG_INITRD_TAG	1
 
 #define	CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT	/* undef this for direct boot from */
+									/* NOR flash without preloader */
 
 #define	CONFIG_SYS_LONGHELP
 
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index f09214d..eab37df 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -41,6 +41,39 @@
 #define CONFIG_INITRD_TAG		1
 
 #define CONFIG_MENUPROMPT		"."
+/*
+ * LowLevel Init
+ */
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
+/* flash */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL	0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 63d07ff..c802dcb 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -37,17 +37,20 @@
 #define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
 #define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
 #define	CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
-#else
-#ifdef XILINX_UART16550_BASEADDR
-#define CONFIG_SYS_NS16550
+#elif XILINX_UART16550_BASEADDR
+#define CONFIG_SYS_NS16550	1
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
 #define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550_COM1	XILINX_UART16550_BASEADDR
+#define CONFIG_SYS_NS16550_COM1	(XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
 #define CONFIG_SYS_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
 #define	CONFIG_BAUDRATE		115200
-#define	CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 115200 }
-#endif
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+#else
+#error Undefined uart
 #endif
 
 /* setting reset address */
@@ -274,6 +277,5 @@
 					"1m(romfs),1m(cramfs),-(jffs2)\0"
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_OF_LIBFDT	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 2ffeae6..fb10616 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -49,33 +49,35 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR	1
 /* flash */
-#define MC_PUIA_VAL	0x00000000
-#define MC_PUP_VAL	0x00000000
-#define MC_PUER_VAL	0x00000000
-#define MC_ASR_VAL	0x00000000
-#define MC_AASR_VAL	0x00000000
-#define EBI_CFGR_VAL	0x00000000
-#define SMC_CSR0_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */
-#define PLLBR_VAL	0x1048bE0E /* 48 MHz (divider by 2 for USB) */
-#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x1048bE0E /* 48 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL	0x00000000
-#define PIOC_PDR_VAL	0xFFFF0000
-#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL	0x3211295A /* set up the SDRAM */
-#define SDRAM		0x20000000 /* address of the SDRAM */
-#define SDRAM1		0x20000020 /* address of the SDRAM */
-#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL	0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1	0x00000004 /* refresh */
-#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x3211295A /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000020 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#else
+#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 9997c9b..5202004 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -31,10 +31,13 @@
 #define CONFIG_MS7722SE		1
 
 #define CONFIG_CMD_FLASH
+#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h
index 0a75794..4d5c1ab 100644
--- a/include/configs/netstal-common.h
+++ b/include/configs/netstal-common.h
@@ -202,8 +202,9 @@
 #define CONFIG_ETHADDR      00:60:13:00:00:00   /* Netstal Machines AG MAC */
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 
-#define CONFIG_SYS_TFTP_LOADADDR 0x01000000
-
+#define CONFIG_SYS_TFTP_LOADADDR	0x01000000
+#define CONFIG_SYS_VXWORKS_ADD_PARAMS	"u=dpu pw=netstal8752"
+#define CONFIG_SYS_VXWORKS_SERVERNAME	"c"
 /*
  * General common environment variables shared by all boards produced by Netstal Maschinen
  */
@@ -223,19 +224,17 @@
 	"fdt_addr_r=800000\0"						\
 	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
 	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
-	"load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"	\
-	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
-		"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"		\
-		"cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};" \
-		"setenv filesize\0"					\
-	"upd=run load update\0"						\
-	"vx_rom=" xstr(CONFIG_HOSTNAME) "/"     			\
-	xstr(CONFIG_HOSTNAME) "_vx_rom\0"				\
-	"vx=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " ${vx_rom};run vxargs;"	\
-	"bootvx\0"							\
-	"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}"	\
-	" h=${serverip} u=dpu pw=netstal8752 "				\
-	"tn=" xstr(CONFIG_HOSTNAME) " f=0x3008\0"			\
+	"uload=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " "		\
+		xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"vx_rom=" xstr(CONFIG_HOSTNAME) "/"				\
+		xstr(CONFIG_HOSTNAME) "_vx_rom\0"			\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"\
+		"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
+		"cp.b ${fileaddr} "xstr(CONFIG_SYS_MONITOR_BASE) 	\
+		" ${filesize}; setenv filesize\0"			\
+	"upd=run uload update\0"					\
+	"vx=setenv bootfile ${vx_rom}; tftp " 				\
+		xstr(CONFIG_SYS_TFTP_LOADADDR) "; bootvx\0"		\
 	CONFIG_NETSTAL_DEF_ENV_ROOTPATH
 
 /*
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index f028d1a..8444462 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -150,7 +150,7 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /* Address and size of Primary Environment Sector */
 #define CONFIG_ENV_SIZE		0x8000
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 174149b..0603e3c 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -162,7 +162,6 @@
 #undef  CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index aefd30a..8141a46 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -59,7 +59,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache */
 #define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
 #define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
 
 /*
@@ -280,7 +279,6 @@
 				| CONFIG_SYS_LBC_LSDMR_RFEN		\
 				)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
@@ -401,25 +399,16 @@
 #define CONFIG_TSEC1_NAME	"eTSEC0"
 #define CONFIG_TSEC2	1
 #define CONFIG_TSEC2_NAME	"eTSEC1"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC2"
-#define CONFIG_TSEC4
-#define CONFIG_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC3_PHY_ADDR		2
-#define TSEC4_PHY_ADDR		3
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
 
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
+
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC2_FLAGS		TSEC_GIGABIT
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME		"eTSEC0"
@@ -466,6 +455,7 @@
 /*
  * Miscellaneous configurable options
  */
+#define CONFIG_CMDLINE_EDITING			/* undef to save memory */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
@@ -509,10 +499,6 @@
 #define CONFIG_ETHADDR	 02:E0:0C:00:00:FD
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR	 02:E0:0C:00:01:FD
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR	 02:E0:0C:00:02:FD
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR	 02:E0:0C:00:03:FD
 #endif
 
 #define CONFIG_IPADDR	 192.168.0.55
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 4301275..d4e9d74 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -69,7 +69,6 @@
 /* below can be toggled for performance analysis. otherwise use default */
 #define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
 #undef	CONFIG_BTB			    /* toggle branch predition	*/
-#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
@@ -180,7 +179,6 @@
 #define CONFIG_SYS_BCSR		((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 45d8179..1008812 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -104,6 +104,9 @@
 #define CONFIG_SYS_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCI2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
 
@@ -241,7 +244,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
@@ -309,18 +311,22 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE	0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_BUS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_VIRT	CONFIG_SYS_PCI1_IO_BUS
 #define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
 
-#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_VIRT	CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE	0xe3000000
-#define CONFIG_SYS_PCI2_IO_PHYS	CONFIG_SYS_PCI2_IO_BASE
+#define CONFIG_SYS_PCI2_IO_BUS	0xe3000000
+#define CONFIG_SYS_PCI2_IO_PHYS	CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_VIRT	CONFIG_SYS_PCI2_IO_BUS
 #define CONFIG_SYS_PCI2_IO_SIZE	0x1000000	/* 16M */
 
 #if defined(CONFIG_PCI)
@@ -407,10 +413,10 @@
  * 0xa000_0000  512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /*
@@ -433,16 +439,27 @@
 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
 /*
  * BAT4         32M    Cache-inhibited, guarded
  * 0xe200_0000  16M    PCI-Express 1 I/O
  * 0xe300_0000  16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
 /*
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index c67db8f..cbf04e3 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -82,7 +82,6 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache		*/
 #define CONFIG_BTB			/* toggle branch predition	*/
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/
 
 #define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
 
@@ -167,7 +166,6 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End used area in RAM	*/
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 2188e54..ae6f45a 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -64,7 +64,6 @@
  */
 #define CONFIG_L2_CACHE                     /* toggle L2 cache         */
 #define  CONFIG_BTB                          /* toggle branch predition */
-#define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
 
 #define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
 
@@ -151,7 +150,6 @@
 #define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
 #define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index b0bd050..c312f1a 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -64,7 +64,6 @@
  */
 #define CONFIG_L2_CACHE				/* toggle L2 cache	       */
 #define  CONFIG_BTB				/* toggle branch predition */
-#define  CONFIG_ADDR_STREAMING			/* toggle addr streaming	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F   1		/* Call board_pre_init	 */
 
@@ -164,7 +163,6 @@
 #define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
 #define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
deleted file mode 100644
index 6a92703..0000000
--- a/include/configs/xupv2p.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * (C) Copyright 2007-2008 Michal Simek
- *
- * Michal SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "../board/xilinx/xupv2p/xparameters.h"
-
-#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
-#define	CONFIG_XUPV2P		1
-
-/* uart */
-#ifdef XILINX_UARTLITE_BASEADDR
-#define	CONFIG_XILINX_UARTLITE
-#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
-#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
-#define	CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
-#else
-#ifdef XILINX_UART16550_BASEADDR
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	4
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550_COM1	XILINX_UART16550_BASEADDR
-#define CONFIG_SYS_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
-#define	CONFIG_BAUDRATE		115200
-#define	CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 115200 }
-#endif
-#endif
-
-/*
- * setting reset address
- *
- * TEXT_BASE is set to place, where the U-BOOT run in RAM, but
- * if you want to store U-BOOT in flash, set CONFIG_SYS_RESET_ADDRESS
- * to FLASH memory and after loading bitstream jump to FLASH.
- * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
- * jump to CONFIG_SYS_RESET_ADDRESS where is the original U-BOOT code.
- */
-/* #define	CONFIG_SYS_RESET_ADDRESS	0x36000000 */
-
-/* ethernet */
-#ifdef XILINX_EMAC_BASEADDR
-#define CONFIG_XILINX_EMAC	1
-#define CONFIG_SYS_ENET
-#else
-#ifdef XILINX_EMACLITE_BASEADDR
-#define CONFIG_XILINX_EMACLITE	1
-#define CONFIG_SYS_ENET
-#endif
-#endif
-#undef ET_DEBUG
-
-/* gpio */
-#ifdef XILINX_GPIO_BASEADDR
-#define	CONFIG_SYS_GPIO_0		1
-#define	CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
-#endif
-
-/* interrupt controller */
-#ifdef XILINX_INTC_BASEADDR
-#define	CONFIG_SYS_INTC_0		1
-#define	CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
-#define	CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
-#endif
-
-/* timer */
-#ifdef XILINX_TIMER_BASEADDR
-#if (XILINX_TIMER_IRQ != -1)
-#define	CONFIG_SYS_TIMER_0		1
-#define	CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
-#define	CONFIG_SYS_TIMER_0_IRQ		XILINX_TIMER_IRQ
-#define	FREQUENCE		XILINX_CLOCK_FREQ
-#define	CONFIG_SYS_TIMER_0_PRELOAD	( FREQUENCE/1000 )
-#endif
-#else
-#ifdef XILINX_CLOCK_FREQ
-#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
-#else
-#error BAD CLOCK FREQ
-#endif
-#endif
-/*
- * memory layout - Example
- * TEXT_BASE = 0x3600_0000;
- * CONFIG_SYS_SRAM_BASE = 0x3000_0000;
- * CONFIG_SYS_SRAM_SIZE = 0x1000_0000;
- *
- * CONFIG_SYS_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
- * CONFIG_SYS_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
- * CONFIG_SYS_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
- *
- * 0x3000_0000	CONFIG_SYS_SDRAM_BASE
- *					FREE
- * 0x3600_0000	TEXT_BASE
- *		U-BOOT code
- * 0x3602_0000
- *					FREE
- *
- *					STACK
- * 0x3FF7_F000	CONFIG_SYS_MALLOC_BASE
- *					MALLOC_AREA	256kB	Alloc
- * 0x3FFB_F000	CONFIG_SYS_MONITOR_BASE
- *					MONITOR_CODE	256kB	Env
- * 0x3FFF_F000	CONFIG_SYS_GBL_DATA_OFFSET
- *					GLOBAL_DATA	4kB	bd, gd
- * 0x4000_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
- */
-
-/* ddr sdram - main memory */
-#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
-#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
-#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
-
-/* global pointer */
-#define	CONFIG_SYS_GBL_DATA_SIZE	0x1000	/* size of global data */
-#define	CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) /* start of global data */
-
-/* monitor code */
-#define	SIZE			0x40000
-#define	CONFIG_SYS_MONITOR_LEN		SIZE
-#define	CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
-#define	CONFIG_SYS_MONITOR_END		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define	CONFIG_SYS_MALLOC_LEN		SIZE
-#define	CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-
-/* stack */
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE
-
-#define	CONFIG_SYS_NO_FLASH		1
-#define	CONFIG_ENV_IS_NOWHERE	1
-#define	CONFIG_ENV_SIZE		0x1000
-#define	CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_IRQ
-
-#ifndef CONFIG_SYS_ENET
-	#undef CONFIG_CMD_NET
-#else
-	#define CONFIG_CMD_PING
-#endif
-
-#ifdef XILINX_SYSACE_BASEADDR
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#endif
-
-/* Miscellaneous configurable options */
-#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
-#define	CONFIG_SYS_CBSIZE	512	/* size of console buffer */
-#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
-#define	CONFIG_SYS_MAXARGS	15	/* max number of command args */
-#define	CONFIG_SYS_LONGHELP
-#define	CONFIG_SYS_LOAD_ADDR	0x12000000 /* default load address */
-
-#define	CONFIG_BOOTDELAY	30
-#define	CONFIG_BOOTARGS		"root=romfs"
-#define	CONFIG_HOSTNAME		"xupv2p"
-#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
-#define	CONFIG_IPADDR		192.168.0.3
-#define	CONFIG_SERVERIP		192.168.0.5
-#define	CONFIG_GATEWAYIP	192.168.0.1
-#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
-
-/* architecture dependent code */
-#define	CONFIG_SYS_USR_EXCEP	/* user exception */
-#define CONFIG_SYS_HZ	1000
-
-#define CONFIG_PREBOOT	"echo U-BOOT by mONStR;"	\
-	"base 0;" \
-	"echo"
-
-/* system ace */
-#ifdef XILINX_SYSACE_BASEADDR
-#define	CONFIG_SYSTEMACE
-/* #define DEBUG_SYSTEMACE */
-#define	SYSTEMACE_CONFIG_FPGA
-#define	CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
-#define	CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
-#define	CONFIG_DOS_PARTITION
-#endif
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_OF_LIBFDT	1 /* flat device tree */
-
-#endif	/* __CONFIG_H */