* Code cleanup:

  - remove trailing white space, trailing empty lines, C++ comments, etc.
  - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)

* Patches by Kenneth Johansson, 25 Jun 2003:
  - major rework of command structure
    (work done mostly by Michal Cendrowski and Joakim Kristiansen)

69 files changed, 746 insertions, 779 deletions

diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index f933ea8..b25e48c 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -106,7 +106,7 @@
 
 /* #define CONFIG_TULIP */
 /* #define CONFIG_EEPRO100 */
-#define CONFIG_NATSEMI  
+#define CONFIG_NATSEMI
 
 #define PCI_ENET0_IOADDR		0x80000000
 #define PCI_ENET0_MEMADDR		0x80000000
@@ -319,6 +319,4 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
index 92b4482..255942a 100644
--- a/include/configs/ADCIOP.h
+++ b/include/configs/ADCIOP.h
@@ -89,7 +89,7 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address	*/
 
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index acb2fb6..632d399 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -67,7 +67,7 @@
 #define	CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS         \
-        (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV)
+	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -99,8 +99,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -120,7 +120,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 4be6158..3868997 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -117,8 +117,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -175,7 +175,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
 #undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -239,7 +239,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
-                                   /* total size of a CAT24WC16 is 2048 bytes */
+				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
@@ -265,7 +265,7 @@
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-                                        /* have only 8kB, 16kB is save here     */
+					/* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
index 009636b..99b42e9 100644
--- a/include/configs/AmigaOneG3SE.h
+++ b/include/configs/AmigaOneG3SE.h
@@ -146,7 +146,7 @@
 /* Size in bytes reserved for initial data
  */
 /* HJF: used to be 0x400000 */
-#define CFG_INIT_RAM_ADDR	0x40000000 
+#define CFG_INIT_RAM_ADDR	0x40000000
 #define CFG_INIT_RAM_END	0x8000
 #define CFG_GBL_DATA_SIZE	128
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -180,9 +180,9 @@
 #define CFG_IBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 /* HJF:
-#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) 
+#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
 #define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) 
+#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
 #define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
 */
 
@@ -191,9 +191,9 @@
 #define CFG_DBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CFG_DBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 /* This used to be commented out */
-#define CFG_IBAT2L	  CFG_DBAT2L 
+#define CFG_IBAT2L	  CFG_DBAT2L
 /* This here too */
-#define CFG_IBAT2U	  CFG_DBAT2U 
+#define CFG_IBAT2U	  CFG_DBAT2U
 
 
 /* I/O and PCI memory at 0xf0000000
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index d312e6b..5dd7a7e 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -71,8 +71,8 @@
 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 
 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
-                                 CFG_CMD_SCSI   | CFG_CMD_IDE | CFG_CMD_DATE  |\
-                                 CFG_CMD_FDC    | CFG_CMD_ELF)
+				 CFG_CMD_SCSI   | CFG_CMD_IDE | CFG_CMD_DATE  |\
+				 CFG_CMD_FDC    | CFG_CMD_ELF)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -319,14 +319,14 @@ extern unsigned char   scsi_sym53c8xx_ccf;
 #define CFG_NS87308                    /* Nat Semi super-io cntr on ISA bus */
 #define CFG_NS87308_BADDR_10    1
 #define CFG_NS87308_DEVS        (CFG_NS87308_UART1   | \
-                                 CFG_NS87308_UART2   | \
-                                 CFG_NS87308_KBC1    | \
-                                 CFG_NS87308_MOUSE   | \
-                                 CFG_NS87308_FDC     | \
-                                 CFG_NS87308_RARP    | \
-                                 CFG_NS87308_GPIO    | \
-                                 CFG_NS87308_POWRMAN | \
-                                 CFG_NS87308_RTC_APC )
+				 CFG_NS87308_UART2   | \
+				 CFG_NS87308_KBC1    | \
+				 CFG_NS87308_MOUSE   | \
+				 CFG_NS87308_FDC     | \
+				 CFG_NS87308_RARP    | \
+				 CFG_NS87308_GPIO    | \
+				 CFG_NS87308_POWRMAN | \
+				 CFG_NS87308_RTC_APC )
 
 #define CFG_NS87308_PS2MOD
 #define CFG_NS87308_GPIO_BASE   0x0220
@@ -431,7 +431,7 @@ extern  unsigned long           bab7xx_get_gclk_freq (void);
  */
 #undef  CFG_L2
 #define L2_INIT     (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-                     L2CR_L2OH_5   | L2CR_L2CTL   | L2CR_L2WT)
+		     L2CR_L2OH_5   | L2CR_L2CTL   | L2CR_L2WT)
 #define L2_ENABLE   (L2_INIT | L2CR_L2E)
 
 #define CFG_L2_BAB7xx
diff --git a/include/configs/BUBINGA405EP.h b/include/configs/BUBINGA405EP.h
index f776a32..99fcbae 100644
--- a/include/configs/BUBINGA405EP.h
+++ b/include/configs/BUBINGA405EP.h
@@ -32,7 +32,6 @@
 /*#define __DEBUG_START_FROM_SRAM__ */
 
 
-
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -220,7 +219,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index 9b8bd05..7aceb58 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -59,7 +59,7 @@
 #define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|       \
 				CFG_CMD_IRQ	|       \
 				CFG_CMD_EEPROM      ) & \
-                               ~CFG_CMD_NET)
+			       ~CFG_CMD_NET)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -91,8 +91,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -153,7 +153,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
index 0fb24db..ba15e91 100644
--- a/include/configs/CCM.h
+++ b/include/configs/CCM.h
@@ -60,10 +60,10 @@
 #undef	CONFIG_BOOTARGS
 
 #define CONFIG_BOOTCOMMAND      "setenv bootargs " \
-                                "mem=$(mem) " \
-                                "root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
-                                "wt_8xx=timeout:3600; " \
-                                "bootm"
+				"mem=$(mem) " \
+				"root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
+				"wt_8xx=timeout:3600; " \
+				"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index d7fbe2e..4be94ed 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -46,10 +46,10 @@
 
 #if 0
 #define CONFIG_PREBOOT                                                          \
-        "crc32 f0207004 ffc 0;"                                                 \
-        "if cmp 0 f0207000 1;"                                                  \
-        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
-        "else;echo Old CRC is bad;fi"
+	"crc32 f0207004 ffc 0;"                                                 \
+	"if cmp 0 f0207000 1;"                                                  \
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+	"else;echo Old CRC is bad;fi"
 #endif
 
 #undef	CONFIG_BOOTARGS
@@ -128,8 +128,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -149,7 +149,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -240,7 +240,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x200   /* 512 bytes may be used for env vars */
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 2671b5f..1f9d39c 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -47,10 +47,10 @@
 
 #if 0
 #define CONFIG_PREBOOT                                                          \
-        "crc32 f0207004 ffc 0;"                                                 \
-        "if cmp 0 f0207000 1;"                                                  \
-        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
-        "else;echo Old CRC is bad;fi"
+	"crc32 f0207004 ffc 0;"                                                 \
+	"if cmp 0 f0207000 1;"                                                  \
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+	"else;echo Old CRC is bad;fi"
 #endif
 
 #undef	CONFIG_BOOTARGS
@@ -135,8 +135,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -160,7 +160,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -251,7 +251,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
-                                   /* total size of a CAT24WC16 is 2048 bytes */
+				   /* total size of a CAT24WC16 is 2048 bytes */
 #endif
 
 #define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
@@ -279,7 +279,7 @@
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-                                        /* have only 8kB, 16kB is save here     */
+					/* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index de55e87..00adfd5 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -48,10 +48,10 @@
 
 #if 0
 #define CONFIG_PREBOOT                                                          \
-        "crc32 f0207004 ffc 0;"                                                 \
-        "if cmp 0 f0207000 1;"                                                  \
-        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
-        "else;echo Old CRC is bad;fi"
+	"crc32 f0207004 ffc 0;"                                                 \
+	"if cmp 0 f0207000 1;"                                                  \
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+	"else;echo Old CRC is bad;fi"
 #endif
 
 #undef	CONFIG_BOOTARGS
@@ -123,8 +123,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -148,7 +148,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -239,7 +239,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars*/
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 #define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
@@ -267,7 +267,7 @@
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-                                        /* have only 8kB, 16kB is save here     */
+					/* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 174b0e5..bcda699 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -90,8 +90,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -111,7 +111,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 #define CFG_PCI_SUBSYS_DEVICEID 0x0404  /* PCI Device ID: CPCI-ISER4    */
@@ -181,7 +181,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 9712d47..390b796 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -361,7 +361,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
-                         HID0_DCI|HID0_IFEM|HID0_ABE)
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 #define CFG_HID2        0
 
@@ -394,10 +394,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP)
+			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -498,55 +498,55 @@
 /* Bank 0 - Boot ROM
  */
 #define CFG_BR0_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-                         BRx_PS_8                       |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxU_EHTR_8IDLE)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
 
 /* Bank 1 - FLASH
  */
 #define CFG_BR1_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxU_EHTR_8IDLE)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
 
 #else /* CONFIG_BOOT_ROM */
 /* Bank 0 - FLASH
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxU_EHTR_8IDLE)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
 
 /* Bank 1 - Boot ROM
  */
 #define CFG_BR1_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
-                         BRx_PS_8                       |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxU_EHTR_8IDLE)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
 
 #endif /* CONFIG_BOOT_ROM */
 
@@ -555,9 +555,9 @@
  */
 #ifndef CFG_RAMBOOT
 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
 
 #define CFG_OR2_PRELIM	 CFG_OR2_9COL
 
@@ -567,88 +567,88 @@
 /* Bank 3 - Dual Ported SRAM
  */
 #define CFG_BR3_PRELIM  ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
-                         BRx_PS_16                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR3_PRELIM  (P2SZ_TO_AM(CFG_DPSRAM_SIZE)    |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_5_CLK                 |\
-                         ORxG_SETA)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
 
 /* Bank 4 - DiskOnChip
  */
 #define CFG_BR4_PRELIM  ((CFG_DOC_BASE & BRx_BA_MSK)    |\
-                         BRx_PS_8                       |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR4_PRELIM  (P2SZ_TO_AM(CFG_DOC_SIZE)       |\
-                         ORxG_ACS_DIV2                  |\
-                         ORxG_SCY_5_CLK                 |\
-                         ORxU_EHTR_8IDLE)
+			 ORxG_ACS_DIV2                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxU_EHTR_8IDLE)
 
 /* Bank 5 - FDC37C78 controller
  */
 #define CFG_BR5_PRELIM  ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
-                         BRx_PS_8                         |\
-                         BRx_MS_GPCM_P                    |\
-                         BRx_V)
+			 BRx_PS_8                         |\
+			 BRx_MS_GPCM_P                    |\
+			 BRx_V)
 
 #define CFG_OR5_PRELIM  (P2SZ_TO_AM(CFG_FDC37C78_SIZE)    |\
-                         ORxG_ACS_DIV2                    |\
-                         ORxG_SCY_8_CLK                   |\
-                         ORxU_EHTR_8IDLE)
+			 ORxG_ACS_DIV2                    |\
+			 ORxG_SCY_8_CLK                   |\
+			 ORxU_EHTR_8IDLE)
 
 /* Bank 6 - Board control registers
  */
 #define CFG_BR6_PRELIM  ((CFG_BCRS_BASE & BRx_BA_MSK)   |\
-                         BRx_PS_8                       |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR6_PRELIM  (P2SZ_TO_AM(CFG_BCRS_SIZE)      |\
-                         ORxG_CSNT                      |\
-                         ORxG_SCY_5_CLK)
+			 ORxG_CSNT                      |\
+			 ORxG_SCY_5_CLK)
 
 /* Bank 7 - VME Extended Access Range
  */
 #define CFG_BR7_PRELIM  ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
-                         BRx_PS_32                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_32                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR7_PRELIM  (P2SZ_TO_AM(CFG_VMEEAR_SIZE)    |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_5_CLK                 |\
-                         ORxG_SETA)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
 
 /* Bank 8 - VME Standard Access Range
  */
 #define CFG_BR8_PRELIM  ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
-                         BRx_PS_16                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR8_PRELIM  (P2SZ_TO_AM(CFG_VMESAR_SIZE)    |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_5_CLK                 |\
-                         ORxG_SETA)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
 
 /* Bank 9 - VME Short I/O Access Range
  */
 #define CFG_BR9_PRELIM  ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
-                         BRx_PS_16                        |\
-                         BRx_MS_GPCM_P                    |\
-                         BRx_V)
+			 BRx_PS_16                        |\
+			 BRx_MS_GPCM_P                    |\
+			 BRx_V)
 
 #define CFG_OR9_PRELIM  (P2SZ_TO_AM(CFG_VMESIOAR_SIZE)    |\
-                         ORxG_CSNT                        |\
-                         ORxG_ACS_DIV1                    |\
-                         ORxG_SCY_5_CLK                   |\
-                         ORxG_SETA)
+			 ORxG_CSNT                        |\
+			 ORxG_ACS_DIV1                    |\
+			 ORxG_SCY_5_CLK                   |\
+			 ORxG_SETA)
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 1bd6899..fd85944 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -46,7 +46,7 @@
 
 /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
  * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
- #define CONFIG_PRAM			16 
+ #define CONFIG_PRAM			16
  */
 #define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
 #undef CONFIG_BOOTARGS
@@ -56,10 +56,10 @@
 #define	CFG_AUTOLOAD		"no"
 #define CONFIG_BOOTCOMMAND	"dhcp"
 
-/* 
+/*
  * ..during experiments..
  #define CONFIG_SERVERIP         10.0.0.1
- #define CONFIG_ETHADDR          00:40:a6:80:14:5 
+ #define CONFIG_ETHADDR          00:40:a6:80:14:5
  */
 #define CONFIG_HARD_I2C         1		/* hardware support for i2c */
 #define CONFIG_SDRAM_BANK0		1
@@ -108,13 +108,13 @@
 	CONFIG_BOOTP_BOOTFILESIZE|\
 	CONFIG_BOOTP_BOOTPATH)
 
-/* 
+/*
  * how many time to fail & restart a net-TFTP before giving up & resetting
  * the board hoping that a reset of net interface might help..
  */
 #define CONFIG_NET_RESET 5
 
-/* 
+/*
  * bauds.  Just to make it compile; in our case, I read the base_baud
  * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
  * drives the system clock.
@@ -168,7 +168,7 @@
 #define CFG_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
 
 /* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
-#define CFG_ENV_OFFSET		0x3c8000 
+#define CFG_ENV_OFFSET		0x3c8000
 #define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
 #define	CFG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
 #define CFG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/
@@ -184,15 +184,15 @@
 #define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
 #define CFG_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
 #define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
-                                + CFG_MALLOC_LEN \
-                                + CFG_ENV_SECT_SIZE \
-                                + CFG_STACK_USAGE )
+				+ CFG_MALLOC_LEN \
+				+ CFG_ENV_SECT_SIZE \
+				+ CFG_STACK_USAGE )
 
 #define CFG_MEMTEST_END		(CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
 /* END ENVIRONNEMENT FLASH */
 
 /*-----------------------------------------------------------------------
- * Cache Configuration.  Only used to ..?? clear it, I guess.. 
+ * Cache Configuration.  Only used to ..?? clear it, I guess..
  */
 #define CFG_DCACHE_SIZE		16384
 #define CFG_CACHELINE_SIZE	32
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
index 229e458..30e978c 100644
--- a/include/configs/DASA_SIM.h
+++ b/include/configs/DASA_SIM.h
@@ -98,7 +98,7 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address	*/
 
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index bac6221..3e5fc3f 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -97,8 +97,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -118,7 +118,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -210,7 +210,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index 54cdd23..7176905 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -319,7 +319,7 @@
 #define L2_INIT     0       /* cpu 750 CXe*/
 #else
 #define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-                     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
+		     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
 #endif
 #define L2_ENABLE   (L2_INIT | L2CR_L2E)
 
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index e9561b9..2f253b9 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -64,20 +64,20 @@
      "echo Type \"run nfsboot\" to mount root filesystem over NFS;"        \
      "echo"
 
-#undef	  CONFIG_BOOTARGS	
+#undef	  CONFIG_BOOTARGS
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
     "ramargs=setenv bootargs root=/dev/ram rw\0"			\
     "rootargs=setenv rootpath /tftp/$(ipaddr)\0"			\
     "nfsargs=setenv bootargs root=/dev/nfs rw "				\
-        "nfsroot=$(serverip):$(rootpath)\0"				\
+	"nfsroot=$(serverip):$(rootpath)\0"				\
     "addip=setenv bootargs $(bootargs) "				\
-        "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"		\
-        ":$(hostname):eth0:off panic=1\0"				\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"		\
+	":$(hostname):eth0:off panic=1\0"				\
     "ramboot=tftp 400000 /home/paugaml/pMulti;"				\
-        "run ramargs;bootm\0"						\
+	"run ramargs;bootm\0"						\
     "nfsboot=tftp 400000 /home/paugaml/uImage;"				\
-        "run rootargs;run nfsargs;run addip;bootm\0"			\
+	"run rootargs;run nfsargs;run addip;bootm\0"			\
     ""
 #define CONFIG_BOOTCOMMAND	"run ramboot"
 
@@ -92,8 +92,8 @@
 #undef	  CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #define CONFIG_COMMANDS	        ( CONFIG_CMD_DFL | \
-                                  CFG_CMD_ASKENV | \
-                                  CFG_CMD_DATE   )
+				  CFG_CMD_ASKENV | \
+				  CFG_CMD_DATE   )
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -212,7 +212,7 @@
  */
 #define CFG_NVRAM_BASE_ADDR     CFG_NVRAM_BASE /* Base address of NVRAM area */
 #define CFG_NVRAM_SIZE          ((128*1024)-8) /* clock regs resident in the */
-                                               /*   8 top NVRAM locations    */
+					       /*   8 top NVRAM locations    */
 
 #if defined(CFG_ENV_IS_IN_NVRAM)
 #  define CFG_ENV_ADDR          CFG_NVRAM_BASE /* Base address of NVRAM area */
@@ -236,10 +236,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
-                         SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
+			 SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
 #else
 #  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
-                                                   SYPCR_SWP)
+						   SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index 9f6baf7..539716f 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -156,7 +156,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
 #undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG	*/
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405GP		*/
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
index 7a8fba6..b176c6f 100644
--- a/include/configs/ESTEEM192E.h
+++ b/include/configs/ESTEEM192E.h
@@ -113,7 +113,6 @@
 #define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
-
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
@@ -301,7 +300,6 @@
 #define CFG_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/
 
 
-
 /*
  * Internal Definitions
  *
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
index b6e1941..137b1a7 100644
--- a/include/configs/ETX094.h
+++ b/include/configs/ETX094.h
@@ -282,7 +282,7 @@
 
 /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0	*/
 #define CFG_OR_TIMING_FLASH    (OR_ACS_DIV2 | OR_BI | \
-                               OR_SCY_2_CLK | OR_TRLX )
+			       OR_SCY_2_CLK | OR_TRLX )
 
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index acd8538..af5122f 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -198,11 +198,11 @@
 #define CFG_DEV2_PAR		0xc0059bd4
 #define CFG_8BIT_BOOT_PAR	0xc00b5e7c
 #define CFG_32BIT_BOOT_PAR	0xc4a8241c
-        /*   c    4    a      8     2     4    1      c		*/
-        /* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
-        /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
-        /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
-        /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+	/*   c    4    a      8     2     4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
 
 #if 0 /* Wrong?? NTL */
 #define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
@@ -229,11 +229,11 @@
 						/* GPP[27:26] Int[1:0] */
 #else
 # define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
-                                                /* GPP[29]    (PCI1Int) */
-                                                /* BClkOut0 */
-                                                /* GPP[27]    (PCI0Int) */
-                                                /* GPP[26]    (RtcInt or PCI1Int) */
-                                                /* CPUInt[25:24] */
+						/* GPP[29]    (PCI1Int) */
+						/* BClkOut0 */
+						/* GPP[27]    (PCI0Int) */
+						/* GPP[26]    (RtcInt or PCI1Int) */
+						/* CPUInt[25:24] */
 #endif
 
 # define CFG_SERIAL_PORT_MUX	0x00000102	/* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
@@ -242,9 +242,9 @@
 # define CFG_GPP_LEVEL_CONTROL	0x000002c6
 #else
 # define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
-                                                /* gpp[29] */
+						/* gpp[29] */
 						/* gpp[27:26] */
-                                                /* gpp[22:21] */
+						/* gpp[22:21] */
 
 # define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
 				/* idmas use buffer 1,1
@@ -295,7 +295,6 @@
 #define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
 
 
-
 /* PCI I/O MAP section */
 #define CFG_PCI0_IO_BASE	0xfa000000
 #define CFG_PCI0_IO_SIZE	_16M
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 47a8786..0702c2c 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -50,7 +50,7 @@
  * generated by the DS1337 - and the DS1337 clock can be turned off.
  */
 #if !defined(CONFIG_SC)
-#define	CONFIG_8xx_GCLK_FREQ			66600000 
+#define	CONFIG_8xx_GCLK_FREQ			66600000
 #else
 #define	CONFIG_8xx_GCLK_FREQ			48000000
 #endif
@@ -204,7 +204,7 @@
  * length of time, so we use an external RTC on the I2C bus instead.
  */
 #define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR				0x68 
+#define CFG_I2C_RTC_ADDR				0x68
 
 #else
 /*
@@ -248,7 +248,7 @@
 								CFG_CMD_POST_DIAG )
 
 #if !defined(CONFIG_SC)
-#define	CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) 
+#define	CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
 #else
 #define CONFIG_COMMANDS	BASE_CONFIG_COMMANDS
 #endif
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index fddf0ca..6490962 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -227,7 +227,7 @@
 			 SIUMCR_DBGC11 | SIUMCR_MLRC10)
 
 /*-----------------------------------------------------------------------
- * Clock Setting - get clock frequency from Board Revision Register 
+ * Clock Setting - get clock frequency from Board Revision Register
  *-----------------------------------------------------------------------
  */
 #ifndef __ASSEMBLY__
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index b924b9c..962a468 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -432,7 +432,6 @@ cp.b 200000 40040000 14000\0"
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
 
-
 #define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
 #if 0
 #define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
index 56ecf0c..4c01cda 100644
--- a/include/configs/LANTEC.h
+++ b/include/configs/LANTEC.h
@@ -297,7 +297,7 @@
 
 /* FLASH timing */
 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
-                                 OR_SCY_5_CLK | OR_TRLX)
+				 OR_SCY_5_CLK | OR_TRLX)
 
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index e62d36c..d6e3fb8 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -72,7 +72,7 @@
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_COMMANDS		( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \
-                              CFG_CMD_PCMCIA | CFG_CMD_IDE )
+			      CFG_CMD_PCMCIA | CFG_CMD_IDE )
 
 #define CONFIG_DOS_PARTITION
 
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index 78caafd..e36341f 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -116,12 +116,12 @@
 #define CONFIG_BR0_WORKAROUND   1
 
 #define CONFIG_COMMANDS	     ( CONFIG_CMD_DFL  | \
-                               CFG_CMD_DATE    | \
-                               CFG_CMD_EEPROM  | \
-                               CFG_CMD_ELF     | \
-                               CFG_CMD_I2C     | \
-                               CFG_CMD_JFFS2   | \
-                               CFG_CMD_REGINFO )
+			       CFG_CMD_DATE    | \
+			       CFG_CMD_EEPROM  | \
+			       CFG_CMD_ELF     | \
+			       CFG_CMD_I2C     | \
+			       CFG_CMD_JFFS2   | \
+			       CFG_CMD_REGINFO )
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 
@@ -225,7 +225,7 @@
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-                         SYPCR_SWP)
+			 SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -265,7 +265,7 @@
 #define MPC8XX_XIN   	5000000L      /* ref clk */
 #define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
 #define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
-                        PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index b29eb8b..8d79307 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -44,7 +44,7 @@
  * CONFIG_BOOT_PCI is only used for first boot-up and should
  * NOT be enabled for production bootloader
  ***********************************************************/
-/*#define        CONFIG_BOOT_PCI         1*/       
+/*#define        CONFIG_BOOT_PCI         1*/
 /***********************************************************
  * Clock
  ***********************************************************/
@@ -260,7 +260,6 @@
 #define CONFIG_PORT_ADDR 	PER_PLD_ADDR + 5
 
 
-
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in On Chip SRAM)
  */
diff --git a/include/configs/ML2.h b/include/configs/ML2.h
index d662661..5fe5d54 100644
--- a/include/configs/ML2.h
+++ b/include/configs/ML2.h
@@ -76,7 +76,6 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
-
 #define CONFIG_COMMANDS	       ( (CONFIG_CMD_DFL & (~CFG_CMD_NET)	 &  \
 				(~CFG_CMD_RTC) & ~(CFG_CMD_PCI)  & ~(CFG_CMD_I2C)) | \
 				CFG_CMD_IRQ	| \
@@ -142,7 +141,6 @@
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
 
-
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 109ed3d..6ad2feb 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -229,7 +229,7 @@
 
 
 #define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
-                                    see 8240 book for details*/
+				    see 8240 book for details*/
 #define PCI_MEM_SPACE1_START	0x80000000
 #define PCI_MEM_SPACE2_START	0xfd000000
 
@@ -296,7 +296,6 @@
 #define CFG_CACHELINE_SIZE  16
 
 
-
 /*
  * Internal Definitions
  *
@@ -328,5 +327,3 @@
 #define CONFIG_TULIP
 
 #endif  /* __CONFIG_H */
-
-
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 9e8d732..8501b2b 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -38,7 +38,7 @@
    !!  0xfff00000						      !!
    !!  The CFG_HRCW_MASTER define below must also be changed to match !!
    !!                                                                 !!
-   !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 
+   !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  */
 
 #ifndef __CONFIG_H
@@ -398,15 +398,15 @@
 /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
 /* #define CFG_HRCW_MASTER 0x0cb23645 */
 
-/* This value should actually be situated in the first 256 bytes of the FLASH  
+/* This value should actually be situated in the first 256 bytes of the FLASH
 	which on the standard MPC8266ADS board is at address 0xFF800000
 	The linker script places it at 0xFFF00000 instead.
 
-	It still works, however, as long as the ADS board jumper JP3 is set to 
-	position 2-3 so the board is using the BCSR as Hardware Configuration Word 
+	It still works, however, as long as the ADS board jumper JP3 is set to
+	position 2-3 so the board is using the BCSR as Hardware Configuration Word
 
-	If you want to use the one defined here instead, ust copy the first 256 bytes from 
-	0xfff00000 to 0xff800000  (for 8MB flash) 
+	If you want to use the one defined here instead, ust copy the first 256 bytes from
+	0xfff00000 to 0xff800000  (for 8MB flash)
 
 	- Rune
 
@@ -514,12 +514,12 @@
 #define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
 #define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
 #define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
-                          	 PICMR_PREFETCH_EN)
+				 PICMR_PREFETCH_EN)
 
-/* 
+/*
  * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI 
- * prefetch, non prefetch, and IO space (see below), must all fit within 
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
  * these windows.
  */
 
@@ -530,7 +530,7 @@
 #define CFG_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
 #define CFG_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (prefetch).
  * This window will be setup with the first set of Outbound ATU registers
  * in the bridge.
@@ -542,7 +542,7 @@
 #define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
 #define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
  * This window will be setup with the second set of Outbound ATU registers
  * in the bridge.
@@ -554,7 +554,7 @@
 #define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 #define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 
-/* 
+/*
  * Master window that allows the CPU to access PCI IO space.
  * This window will be setup with the third set of Outbound ATU registers
  * in the bridge.
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index 03765a3..da52e0e 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -292,6 +292,4 @@
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
index d10fa8f..49bdc45 100644
--- a/include/configs/MVS1.h
+++ b/include/configs/MVS1.h
@@ -184,7 +184,7 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-             SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+	     SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
 #define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 0ac456a..fb3b642 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -95,8 +95,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -116,7 +116,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -188,7 +188,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -240,32 +240,32 @@
 
 /* Memory Bank 2 (PLD - FPGA-boot) initialization                               */
 #define CFG_EBC_PB2AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 3 (PLD - OSL) initialization                                     */
 #define CFG_EBC_PB3AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB3CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 4 (Spartan2 1) initialization                                    */
 #define CFG_EBC_PB4AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB4CR           0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 5 (Spartan2 2) initialization                                    */
 #define CFG_EBC_PB5AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB5CR           0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 6 (Virtex 1) initialization                                      */
 #define CFG_EBC_PB6AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB6CR           0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 7 (Virtex 2) initialization                                      */
 #define CFG_EBC_PB7AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB7CR           0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index 7c161c6..5da3fc5 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -95,8 +95,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -116,7 +116,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_ADAPTER /* select pci adapter          */
 #undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -186,7 +186,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -238,32 +238,32 @@
 
 /* Memory Bank 2 (PLD - FPGA-boot) initialization                               */
 #define CFG_EBC_PB2AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 3 (PLD - OSL) initialization                                     */
 #define CFG_EBC_PB3AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB3CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 4 (Spartan2 1) initialization                                    */
 #define CFG_EBC_PB4AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB4CR           0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 5 (Spartan2 2) initialization                                    */
 #define CFG_EBC_PB5AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB5CR           0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
 
 /* Memory Bank 6 (Virtex 1) initialization                                      */
 #define CFG_EBC_PB6AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB6CR           0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
 
 /* Memory Bank 7 (Virtex 2) initialization                                      */
 #define CFG_EBC_PB7AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-                                            /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
 #define CFG_EBC_PB7CR           0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index b1ed0cb..8ab253a 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -47,10 +47,10 @@
 
 #if 0
 #define CONFIG_PREBOOT                                                          \
-        "crc32 f0207004 ffc 0;"                                                 \
-        "if cmp 0 f0207000 1;"                                                  \
-        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
-        "else;echo Old CRC is bad;fi"
+	"crc32 f0207004 ffc 0;"                                                 \
+	"if cmp 0 f0207000 1;"                                                  \
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+	"else;echo Old CRC is bad;fi"
 #endif
 
 #undef	CONFIG_BOOTARGS
@@ -60,8 +60,8 @@
 #else
 #define CONFIG_BOOTCOMMAND							\
 	"mw.l 0 ffffffff; mw.l 4 ffffffff;"                                     \
-        "while cmp 0 4 1; do echo Waiting for Host...;done;"                    \
-        "bootm 400000"
+	"while cmp 0 4 1; do echo Waiting for Host...;done;"                    \
+	"bootm 400000"
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -123,8 +123,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -144,7 +144,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_ADAPTER /* select pci host function    */
 #undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -218,7 +218,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars*/
-                                   /* total size of a CAT24WC08 is 1024 bytes */
+				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 #define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index 3eb6ac3..645cdc5 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -56,7 +56,7 @@
 #define CONFIG_BOOTDELAY	5
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-			         CONFIG_BOOTP_BOOTFILESIZE)
+				 CONFIG_BOOTP_BOOTFILESIZE)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -231,7 +231,7 @@
  */
 #undef CFG_L2
 #define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
-                   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #define L2_ENABLE (L2_INIT | L2CR_L2E)
 
 /*
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index f4dfbfe..4953458 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -278,6 +278,4 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ISO_PARTITION
 
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 8fbbe30..60e5a9a 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -239,7 +239,6 @@
 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 
 
-
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in On Chip SRAM)
  */
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 6ba14af..6668578 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -347,7 +347,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-                                HID0_IFEM|HID0_ABE)
+				HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
 #define CFG_HID2        0
 
@@ -385,10 +385,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP)
+			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -482,16 +482,16 @@
  * Bank 0 - Flash (64 bit wide)
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxG_EHTR                      |\
-                         ORxG_TRLX)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
 
 /*
  * Bank 1 - Disk-On-Chip
@@ -515,43 +515,43 @@
 #define CFG_PSRT        0x0F
 #ifndef CFG_RAMBOOT
 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
 
 	/* SDRAM initialization values for 8-column chips
 	 */
 #define CFG_OR2_8COL    (CFG_MIN_AM_MASK	        |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI0_A9             |\
-                         ORxS_NUMR_12)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A9             |\
+			 ORxS_NUMR_12)
 
 #define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
-                         PSDMR_BSMA_A14_A16             |\
-                         PSDMR_SDA10_PBI0_A10           |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_1W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_1C                   |\
-                         PSDMR_CL_2)
+			 PSDMR_BSMA_A14_A16             |\
+			 PSDMR_SDA10_PBI0_A10           |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_1W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_1C                   |\
+			 PSDMR_CL_2)
 
 	/* SDRAM initialization values for 9-column chips
 	 */
 #define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI0_A7             |\
-                         ORxS_NUMR_13)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A7             |\
+			 ORxS_NUMR_13)
 
 #define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
-                         PSDMR_BSMA_A13_A15             |\
-                         PSDMR_SDA10_PBI0_A9            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_1W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_1C                   |\
-                         PSDMR_CL_2)
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI0_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_1W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_1C                   |\
+			 PSDMR_CL_2)
 
 #define CFG_OR2_PRELIM   CFG_OR2_9COL
 #define CFG_PSDMR        CFG_PSDMR_9COL
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index e3d3785..54b53bc 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -119,8 +119,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -144,7 +144,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #undef CONFIG_PCI_SCAN_SHOW             /* print pci devices @ startup  */
 
@@ -197,7 +197,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
-                                   /* total size of a CAT24WC16 is 2048 bytes */
+				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
@@ -223,7 +223,7 @@
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-                                        /* have only 8kB, 16kB is save here     */
+					/* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index f20b8f9..959ee1a 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -182,7 +182,7 @@
 #define	CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE	0xFF000000
 
-#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) 
+#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
 #define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
 #define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
@@ -370,8 +370,8 @@
 
 /* ECCX CS settings                                                          */
 #define SED13806_OR             0xFFC00108     /* - 4 Mo
-                                                   - Burst inhibit
-                                                   - external TA             */
+						   - Burst inhibit
+						   - external TA             */
 #define SED13806_REG_ADDR       0xa0000000
 #define SED13806_ACCES          0x801           /* 16 bit access             */
 
@@ -391,8 +391,8 @@
 
 /* Definitions for CSR8                                                      */
 #define ECCX_ENEPSON            0x80    /* Bit 0:
-                                           0= disable and reset SED1386
-                                           1= enable SED1386                 */
+					   0= disable and reset SED1386
+					   1= enable SED1386                 */
 /* Bit 1:   0= SED1386 in Big Endian mode                                    */
 /*          1= SED1386 in little endian mode                                 */
 #define ECCX_LE                 0x40
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index c364672..0abff11 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -226,18 +226,18 @@
 
 /* get the HRCW ISB field from CFG_IMMR */
 #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
-                            ((CFG_IMMR & 0x01000000) >> 7)  |\
-                            ((CFG_IMMR & 0x00100000) >> 4) )
+			    ((CFG_IMMR & 0x01000000) >> 7)  |\
+			    ((CFG_IMMR & 0x00100000) >> 4) )
 
 #define CFG_HRCW_MASTER (HRCW_BPS11                           |\
-                         HRCW_DPPC11                          |\
-                         CFG_SBC_HRCW_IMMR                    |\
-                         HRCW_MMR00                           |\
-                         HRCW_LBPC11                          |\
-                         HRCW_APPC10                          |\
-                         HRCW_CS10PC00                        |\
-                         (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
-                         CFG_SBC_HRCW_BOOT_FLAGS)
+			 HRCW_DPPC11                          |\
+			 CFG_SBC_HRCW_IMMR                    |\
+			 HRCW_MMR00                           |\
+			 HRCW_LBPC11                          |\
+			 HRCW_APPC10                          |\
+			 HRCW_CS10PC00                        |\
+			 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
+			 CFG_SBC_HRCW_BOOT_FLAGS)
 
 /* no slaves */
 #define CFG_HRCW_SLAVE1 0
@@ -358,8 +358,8 @@
  */
 
 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
-                         SIUMCR_APPC10  |\
-                         SIUMCR_CS10PC01)
+			 SIUMCR_APPC10  |\
+			 SIUMCR_CS10PC01)
 
 
 /*-----------------------------------------------------------------------
@@ -369,11 +369,11 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #define CFG_SYPCR       (SYPCR_SWTC |\
-                         SYPCR_BMT  |\
-                         SYPCR_PBME |\
-                         SYPCR_LBME |\
-                         SYPCR_SWRI |\
-                         SYPCR_SWP)
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP)
 
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control                     4-40
@@ -382,9 +382,9 @@
  * and enable Time Counter
  */
 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
-                         TMCNTSC_ALR |\
-                         TMCNTSC_TCF |\
-                         TMCNTSC_TCE)
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -393,8 +393,8 @@
  * Periodic timer
  */
 #define CFG_PISCR       (PISCR_PS  |\
-                         PISCR_PTF |\
-                         PISCR_PTE)
+			 PISCR_PTF |\
+			 PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
@@ -431,29 +431,29 @@
  *
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-                         BRx_PS_64                      |\
+			 BRx_PS_64                      |\
 			 BRx_DECC_NONE                  |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_6_CLK                 |\
-                         ORxG_EHTR)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_6_CLK                 |\
+			 ORxG_EHTR)
 
 /* Bank 1 - SDRAM
  *
  */
 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
 
 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI0_A8             |\
-                         ORxS_NUMR_12                   |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A8             |\
+			 ORxS_NUMR_12                   |\
 			 ORxS_IBID)
 
 #define CFG_PSDMR       0x014DA412
@@ -464,14 +464,14 @@
  *
  */
 #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
-                         BRx_PS_32                      |\
-                         BRx_MS_SDRAM_L                 |\
-                         BRx_V)
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_L                 |\
+			 BRx_V)
 
 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI0_A9             |\
-                         ORxS_NUMR_12)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A9             |\
+			 ORxS_NUMR_12)
 
 #define CFG_LSDMR       0x0169A512
 #define CFG_LSRT	0x79
@@ -482,15 +482,15 @@
  *
  */
 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
-                           BRx_PS_8                     |\
-                           BRx_MS_GPCM_P                |\
-                           BRx_V)
+			   BRx_PS_8                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
 
 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
-                           ORxG_CSNT                   |\
-                           ORxG_ACS_DIV1               |\
-                           ORxG_SCY_5_CLK              |\
-                           ORxG_TRLX)
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
+			   ORxG_SCY_5_CLK              |\
+			   ORxG_TRLX)
 
 /*
  * Internal Definitions
@@ -501,5 +501,3 @@
 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 
 #endif  /* __CONFIG_H */
-
-
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index a1327e7..926d63a 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -135,7 +135,6 @@
 #endif	/* CONFIG_SOFT_I2C */
 
 
-
 #define CONFIG_COMMANDS	    ( ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_I2C	| \
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index 0dd46a0..e4533b4 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -287,10 +287,10 @@
  */
 #if defined(CONFIG_266MHz)
 #define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-				                              HRCW_MODCK_H0111)
+							      HRCW_MODCK_H0111)
 #elif defined(CONFIG_300MHz)
 #define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-				                              HRCW_MODCK_H0110)
+							      HRCW_MODCK_H0110)
 #else
 #define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 #endif
@@ -367,7 +367,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-                                HID0_IFEM|HID0_ABE)
+				HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 #define CFG_HID2        0
 
@@ -409,10 +409,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP)
+			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -490,16 +490,16 @@
 /* Bank 0 - FLASH
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxG_EHTR                      |\
-                         ORxG_TRLX)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
 
 	/* SDRAM on TQM8260 can have either 8 or 9 columns.
 	 * The number affects configuration values.
@@ -511,9 +511,9 @@
 #define CFG_LSRT        0x20
 #ifndef CFG_RAMBOOT
 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
 
 #define CFG_OR1_PRELIM	CFG_OR1_8COL
 
@@ -521,48 +521,48 @@
 	/* SDRAM initialization values for 8-column chips
 	 */
 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A7             |\
-                         ORxS_NUMR_12)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7             |\
+			 ORxS_NUMR_12)
 
 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A15_IS_A5           |\
-                         PSDMR_BSMA_A12_A14             |\
-                         PSDMR_SDA10_PBI1_A8            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_EAMUX                    |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
 
 	/* SDRAM initialization values for 9-column chips
 	 */
 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A5             |\
-                         ORxS_NUMR_13)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A5             |\
+			 ORxS_NUMR_13)
 
 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A16_IS_A5           |\
-                         PSDMR_BSMA_A12_A14             |\
-                         PSDMR_SDA10_PBI1_A7            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_EAMUX                    |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A7            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
 
 /* Bank 2 - Local bus SDRAM
  */
 #ifdef CFG_INIT_LOCAL_SDRAM
 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-                         BRx_PS_32                      |\
-                         BRx_MS_SDRAM_L                 |\
-                         BRx_V)
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_L                 |\
+			 BRx_V)
 
 #define CFG_OR2_PRELIM	CFG_OR2_8COL
 
@@ -571,40 +571,40 @@
 	/* SDRAM initialization values for 8-column chips
 	 */
 #define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A8             |\
-                         ORxS_NUMR_12)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A8             |\
+			 ORxS_NUMR_12)
 
 #define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A15_IS_A5           |\
-                         PSDMR_BSMA_A13_A15             |\
-                         PSDMR_SDA10_PBI1_A9            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_BL                       |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
 
 	/* SDRAM initialization values for 9-column chips
 	 */
 #define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A6             |\
-                         ORxS_NUMR_13)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_13)
 
 #define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A16_IS_A5           |\
-                         PSDMR_BSMA_A13_A15             |\
-                         PSDMR_SDA10_PBI1_A8            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_BL                       |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
 
 #endif /* CFG_INIT_LOCAL_SDRAM */
 
@@ -708,4 +708,3 @@
 
 
 #endif	/* __CONFIG_H */
-
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index 1ea9a5e..2961a6a 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -394,7 +394,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-                                HID0_IFEM|HID0_ABE)
+				HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 #define CFG_HID2        0
 
@@ -436,10 +436,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP)
+			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -517,16 +517,16 @@
 /* Bank 0 - FLASH
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxG_EHTR                      |\
-                         ORxG_TRLX)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
 
 	/* SDRAM on TQM8260 can have either 8 or 9 columns.
 	 * The number affects configuration values.
@@ -538,9 +538,9 @@
 #define CFG_LSRT        0x20
 #ifndef CFG_RAMBOOT
 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
 
 #define CFG_OR1_PRELIM	CFG_OR1_8COL
 
@@ -548,48 +548,48 @@
 	/* SDRAM initialization values for 8-column chips
 	 */
 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A7             |\
-                         ORxS_NUMR_12)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7             |\
+			 ORxS_NUMR_12)
 
 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A15_IS_A5           |\
-                         PSDMR_BSMA_A12_A14             |\
-                         PSDMR_SDA10_PBI1_A8            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_EAMUX                    |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
 
 	/* SDRAM initialization values for 9-column chips
 	 */
 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A5             |\
-                         ORxS_NUMR_13)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A5             |\
+			 ORxS_NUMR_13)
 
 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A16_IS_A5           |\
-                         PSDMR_BSMA_A12_A14             |\
-                         PSDMR_SDA10_PBI1_A7            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_EAMUX                    |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A7            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
 
 /* Bank 2 - Local bus SDRAM
  */
 #ifdef CFG_INIT_LOCAL_SDRAM
 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-                         BRx_PS_32                      |\
-                         BRx_MS_SDRAM_L                 |\
-                         BRx_V)
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_L                 |\
+			 BRx_V)
 
 #define CFG_OR2_PRELIM	CFG_OR2_8COL
 
@@ -598,40 +598,40 @@
 	/* SDRAM initialization values for 8-column chips
 	 */
 #define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A8             |\
-                         ORxS_NUMR_12)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A8             |\
+			 ORxS_NUMR_12)
 
 #define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A15_IS_A5           |\
-                         PSDMR_BSMA_A13_A15             |\
-                         PSDMR_SDA10_PBI1_A9            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_BL                       |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
 
 	/* SDRAM initialization values for 9-column chips
 	 */
 #define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A6             |\
-                         ORxS_NUMR_13)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_13)
 
 #define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A16_IS_A5           |\
-                         PSDMR_BSMA_A13_A15             |\
-                         PSDMR_SDA10_PBI1_A8            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_BL                       |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_CL_2)
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
 
 #endif /* CFG_INIT_LOCAL_SDRAM */
 
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index b5610c9..7ae1c70 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -323,4 +323,3 @@
 #define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/
 
 #endif	/* __CONFIG_H */
-
diff --git a/include/configs/WALNUT405.h b/include/configs/WALNUT405.h
index 36674db..cdc9a3c 100644
--- a/include/configs/WALNUT405.h
+++ b/include/configs/WALNUT405.h
@@ -161,7 +161,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
index 541cf92..3fde238 100644
--- a/include/configs/ZUMA.h
+++ b/include/configs/ZUMA.h
@@ -207,7 +207,6 @@
 	/*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
 
 
-
 #define CFG_8BIT_BOOT_PAR	0xc00b5e7c
 
 #define CFG_MPP_CONTROL_0	0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index e382977..415b7fb 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -49,19 +49,19 @@
 
 #undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
 
-#define CONFIG_BOOTDELAY      3  
+#define CONFIG_BOOTDELAY      3
 /* #define CONFIG_ENV_OVERWRITE  1 */
 
 #define CONFIG_COMMANDS		\
 		       ((CONFIG_CMD_DFL	| \
 			CFG_CMD_DHCP ) & \
-                      ~(CFG_CMD_BDI | \
-                        CFG_CMD_IMI | \
-                        CFG_CMD_AUTOSCRIPT | \
-                        CFG_CMD_FPGA | \
-                        CFG_CMD_MISC | \
-                        CFG_CMD_LOADS ))
-                     
+		      ~(CFG_CMD_BDI | \
+			CFG_CMD_IMI | \
+			CFG_CMD_AUTOSCRIPT | \
+			CFG_CMD_FPGA | \
+			CFG_CMD_MISC | \
+			CFG_CMD_LOADS ))
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -155,7 +155,7 @@ struct bd_info_ext
 #endif
 
 #define	CFG_HZ AT91C_MASTER_CLOCK/2  /* AT91C_TC0_CMR is implicitly set to
-                                        AT91C_TC_TIMER_DIV1_CLOCK */
+					AT91C_TC_TIMER_DIV1_CLOCK */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/atc.h b/include/configs/atc.h
index 1fb6ed8..2751248 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -299,7 +299,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
-                         HID0_DCI|HID0_IFEM|HID0_ABE)
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 #define CFG_HID2        0
 
@@ -332,10 +332,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP)
+			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -437,24 +437,24 @@
 /* Bank 0 - FLASH
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_16                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxU_EHTR_8IDLE)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
 
 
 /* Bank 2 - 60x bus SDRAM
  */
 #ifndef CFG_RAMBOOT
 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
 
 #define CFG_OR2_PRELIM	 CFG_OR2_8COL
 
@@ -462,12 +462,12 @@
 #endif /* CFG_RAMBOOT */
 
 #define CFG_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
-                         BRx_PS_8                       |\
-                         BRx_MS_UPMA                    |\
-                         BRx_V)
+			 BRx_PS_8                       |\
+			 BRx_MS_UPMA                    |\
+			 BRx_V)
 
 #define CFG_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
-									   
+
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index e8b3eb5..e459919 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -17,13 +17,13 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, 
+ * Foundation,
  */
 
 /*
  * File:		cmi_mpc5xx.h
- * 
- * Discription:		Config header file for cmi 
+ *
+ * Discription:		Config header file for cmi
  * 			board  using an MPC5xx CPU
  *
  */
@@ -63,12 +63,12 @@
 
 #define CONFIG_WATCHDOG				/* turn on platform specific watchdog 	*/
 
-#define CONFIG_STATUS_LED	1		/* Enable status led */ 
+#define CONFIG_STATUS_LED	1		/* Enable status led */
 
 #define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
 
 /*
- * Miscellaneous configurable options 
+ * Miscellaneous configurable options
  */
 
 #define	CFG_LONGHELP				/* undef to save memory		*/
@@ -104,7 +104,7 @@
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */       
+#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */
 #define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)       		/* Physical end adress of internal MPC555 used RAM area	*/
 #define	CFG_GBL_DATA_SIZE	64					/* Size in bytes reserved for initial global data */
 #define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
@@ -135,9 +135,9 @@
 
 
 /*-----------------------------------------------------------------------
- * FLASH organization 
+ * FLASH organization
  *-----------------------------------------------------------------------
- * 
+ *
  */
 
 #define CFG_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
@@ -154,7 +154,7 @@
 #endif
 
 /*-----------------------------------------------------------------------
- * SYPCR - System Protection Control			
+ * SYPCR - System Protection Control
  * SYPCR can only be written once after reset!
  *-----------------------------------------------------------------------
  * SW Watchdog freeze
@@ -164,7 +164,7 @@
 			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 #else
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWP)		
+			 SYPCR_SWP)
 #endif	/* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -202,30 +202,30 @@
  * PLPRCR - PLL, Low-Power, and Reset Control Register
  *-----------------------------------------------------------------------
  * Set all bits to 40 Mhz
- * 
+ *
  */
 #define CFG_OSC_CLK   	((uint)4000000) 	/* Oscillator clock is 4MHz 	*/
 #define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
-	
+
 
 /*-----------------------------------------------------------------------
  * UMCR - UIMB Module Configuration Register
  *-----------------------------------------------------------------------
- * 
+ *
  */
 #define CFG_UMCR	(UMCR_FSPEED) 		/* IMB clock same as U-bus 	*/
 
 /*-----------------------------------------------------------------------
  * ICTRL - I-Bus Support Control Register
  */
-#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/ 
+#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/
 
 /*-----------------------------------------------------------------------
  * USIU - Memory Controller Register
- *----------------------------------------------------------------------- 
+ *-----------------------------------------------------------------------
  */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)		
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
 #define CFG_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
 #define CFG_BR1_PRELIM		(ANYBUS_BASE)
 #define CFG_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
@@ -238,7 +238,7 @@
 #define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
 
 /*-----------------------------------------------------------------------
- * DER - Timer Decrementer 
+ * DER - Timer Decrementer
  *-----------------------------------------------------------------------
  * Initialise to zero
  */
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 5a215e4..13996d4 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -100,7 +100,7 @@
 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 #define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 
-                                                /* valid baudrates */
+						/* valid baudrates */
 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index a257b82..879607c 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -122,7 +122,7 @@
 
 #define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
 
-                                                /* valid baudrates */
+						/* valid baudrates */
 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index b933be9..f1b2cc1 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -370,11 +370,11 @@
 /* get the HRCW ISB field from CFG_IMMR */
 /*
 #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
-                            ((CFG_IMMR & 0x01000000) >> 7)  |\
-                            ((CFG_IMMR & 0x00100000) >> 4) )
+			    ((CFG_IMMR & 0x01000000) >> 7)  |\
+			    ((CFG_IMMR & 0x00100000) >> 4) )
 
 #define CFG_HRCW_MASTER (HRCW_EBM                |\
-		         HRCW_L2CPC01            |\
+			 HRCW_L2CPC01            |\
 			 CFG_SBC_HRCW_IMMR       |\
 			 HRCW_APPC10             |\
 			 HRCW_CS10PC01           |\
@@ -512,8 +512,8 @@
  */
 
 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
-                         SIUMCR_APPC10  |\
-                         SIUMCR_CS10PC01)
+			 SIUMCR_APPC10  |\
+			 SIUMCR_CS10PC01)
 
 
 /*-----------------------------------------------------------------------
@@ -524,15 +524,15 @@
  */
 #ifdef CFG_LSDRAM
 #define CFG_SYPCR       (SYPCR_SWTC |\
-                         SYPCR_BMT  |\
-                         SYPCR_PBME |\
-                         SYPCR_LBME |\
-                         SYPCR_SWP)
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWP)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC |\
-                         SYPCR_BMT  |\
-                         SYPCR_PBME |\
-                         SYPCR_SWP)
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_SWP)
 #endif
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control                     4-40
@@ -541,9 +541,9 @@
  * and enable Time Counter
  */
 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
-                         TMCNTSC_ALR |\
-                         TMCNTSC_TCF |\
-                         TMCNTSC_TCE)
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -552,8 +552,8 @@
  * Periodic timer
  */
 /*#define CFG_PISCR       (PISCR_PS  |\
-                         PISCR_PTF |\
-                         PISCR_PTE)*/
+			 PISCR_PTF |\
+			 PISCR_PTE)*/
 #define CFG_PISCR	0
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
@@ -604,29 +604,29 @@
  *
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-                         BRx_PS_64                      |\
+			 BRx_PS_64                      |\
 			 BRx_DECC_NONE                  |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
 
 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
-		         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_6_CLK                 |\
-                         ORxG_EHTR)
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_6_CLK                 |\
+			 ORxG_EHTR)
 
 /* Bank 1 - SDRAM
  * PSDRAM
  */
 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
 
 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A6             |\
-                         ORxS_NUMR_12)
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_12)
 
 #define CFG_PSDMR       0xC34E2462
 #define CFG_PSRT	0x64
@@ -638,14 +638,14 @@
  */
 
   #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
-                           BRx_PS_32                      |\
-                           BRx_MS_SDRAM_L                 |\
-                           BRx_V)
+			   BRx_PS_32                      |\
+			   BRx_MS_SDRAM_L                 |\
+			   BRx_V)
 
   #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
-                           ORxS_BPD_4                     |\
-                           ORxS_ROWST_PBI0_A9             |\
-                           ORxS_NUMR_12)
+			   ORxS_BPD_4                     |\
+			   ORxS_ROWST_PBI0_A9             |\
+			   ORxS_NUMR_12)
 
   #define CFG_LSDMR       0x416A2562
   #define CFG_LSRT	0x64
@@ -657,15 +657,15 @@
  * NVRTC and BCSR
  */
 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
-                           BRx_PS_8                     |\
-                           BRx_MS_GPCM_P                |\
-                           BRx_V)
+			   BRx_PS_8                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
 /*
 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
-                           ORxG_CSNT                   |\
-                           ORxG_ACS_DIV1               |\
-                           ORxG_SCY_10_CLK              |\
-                           ORxG_TRLX)
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
+			   ORxG_SCY_10_CLK              |\
+			   ORxG_TRLX)
 */
 #define CFG_OR4_PRELIM 0xfff00854
 
@@ -673,15 +673,15 @@
  * PCMCIA (currently not working!)
  */
 #define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
-                           BRx_PS_16                     |\
-                           BRx_MS_GPCM_P                |\
-                           BRx_V)
+			   BRx_PS_16                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
 
 #define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
-                           ORxG_CSNT                   |\
-                           ORxG_ACS_DIV1               |\
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
 			   ORxG_SETA                   |\
-                           ORxG_SCY_10_CLK)
+			   ORxG_SCY_10_CLK)
 
 /*
  * Internal Definitions
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 0e9a4ec..3666bdb 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -219,10 +219,10 @@
 #define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
 
 #define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
-            else            iop->pdat &= ~0x00400000
+	    else            iop->pdat &= ~0x00400000
 
 #define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
-            else    iop->pdat &= ~0x00200000
+	    else    iop->pdat &= ~0x00200000
 
 #define MIIDELAY    udelay(1)
 #endif  /* CONFIG_ETHER_ON_FCC */
@@ -291,8 +291,8 @@
  *  - DNS
  */
 #define CONFIG_BOOTP_MASK   (CONFIG_BOOTP_DEFAULT | \
-                             CONFIG_BOOTP_BOOTFILESIZE | \
-                             CONFIG_BOOTP_DNS)
+			     CONFIG_BOOTP_BOOTFILESIZE | \
+			     CONFIG_BOOTP_DNS)
 
 /* undef this to save memory */
 #define CFG_LONGHELP
@@ -302,13 +302,13 @@
 
 /* What U-Boot subsytems do you want enabled? */
 #define CONFIG_COMMANDS     (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
-                               CFG_CMD_BEDBUG  | \
-                               CFG_CMD_ELF | \
-                               CFG_CMD_ASKENV  | \
-                               CFG_CMD_ECHO    | \
-                               CFG_CMD_REGINFO | \
-                               CFG_CMD_IMMAP   | \
-                               CFG_CMD_MII)
+			       CFG_CMD_BEDBUG  | \
+			       CFG_CMD_ELF | \
+			       CFG_CMD_ASKENV  | \
+			       CFG_CMD_ECHO    | \
+			       CFG_CMD_REGINFO | \
+			       CFG_CMD_IMMAP   | \
+			       CFG_CMD_MII)
 
 /* Where do the internal registers live? */
 #define CFG_IMMR        0xf0000000
@@ -367,12 +367,12 @@
 #define CFG_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
 
 #define CFG_MEM_END_USAGE   ( CFG_MONITOR_LEN \
-                            + CFG_MALLOC_LEN \
-                            + CFG_ENV_SECT_SIZE \
-                            + CFG_STACK_USAGE )
+			    + CFG_MALLOC_LEN \
+			    + CFG_ENV_SECT_SIZE \
+			    + CFG_STACK_USAGE )
 
 #define CFG_MEMTEST_END     ( CFG_SDRAM_SIZE * 1024 * 1024 \
-                            - CFG_MEM_END_USAGE )
+			    - CFG_MEM_END_USAGE )
 
 /* valid baudrates */
 #define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
@@ -399,18 +399,18 @@
 
 /* get the HRCW ISB field from CFG_IMMR */
 #define CFG_SBC_HRCW_IMMR   ( ((CFG_IMMR & 0x10000000) >> 10) | \
-                  ((CFG_IMMR & 0x01000000) >>  7) | \
-                  ((CFG_IMMR & 0x00100000) >>  4) )
+		  ((CFG_IMMR & 0x01000000) >>  7) | \
+		  ((CFG_IMMR & 0x00100000) >>  4) )
 
 #define CFG_HRCW_MASTER     ( HRCW_BPS11                | \
-                  HRCW_DPPC11               | \
-                  CFG_SBC_HRCW_IMMR         | \
-                  HRCW_MMR00                | \
-                  HRCW_LBPC11               | \
-                  HRCW_APPC10               | \
-                  HRCW_CS10PC00             | \
-                  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
-                  CFG_SBC_HRCW_BOOT_FLAGS )
+		  HRCW_DPPC11               | \
+		  CFG_SBC_HRCW_IMMR         | \
+		  HRCW_MMR00                | \
+		  HRCW_LBPC11               | \
+		  HRCW_APPC10               | \
+		  HRCW_CS10PC00             | \
+		  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
+		  CFG_SBC_HRCW_BOOT_FLAGS )
 
 /* no slaves */
 #define CFG_HRCW_SLAVE1     0
@@ -488,16 +488,16 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE  |\
-                         HID0_DCE  |\
-                         HID0_ICFI |\
-                         HID0_DCI  |\
-                         HID0_IFEM |\
-                         HID0_ABE)
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
 
 #define CFG_HID0_FINAL  (HID0_ICE  |\
-                         HID0_IFEM |\
-                         HID0_ABE  |\
-                         HID0_EMCP)
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
 #define CFG_HID2    0
 
 /*-----------------------------------------------------------------------
@@ -517,9 +517,9 @@
  *-----------------------------------------------------------------------
  */
 #define CFG_SIUMCR  (SIUMCR_DPPC11  |\
-                     SIUMCR_L2CPC00 |\
-                     SIUMCR_APPC10  |\
-                     SIUMCR_MMR00)
+		     SIUMCR_L2CPC00 |\
+		     SIUMCR_APPC10  |\
+		     SIUMCR_MMR00)
 
 
 /*-----------------------------------------------------------------------
@@ -529,11 +529,11 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #define CFG_SYPCR   (SYPCR_SWTC |\
-                     SYPCR_BMT  |\
-                     SYPCR_PBME |\
-                     SYPCR_LBME |\
-                     SYPCR_SWRI |\
-                     SYPCR_SWP)
+		     SYPCR_BMT  |\
+		     SYPCR_PBME |\
+		     SYPCR_LBME |\
+		     SYPCR_SWRI |\
+		     SYPCR_SWP)
 
 /*-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control             4-40
@@ -542,9 +542,9 @@
  * and enable Time Counter
  */
 #define CFG_TMCNTSC (TMCNTSC_SEC |\
-                     TMCNTSC_ALR |\
-                     TMCNTSC_TCF |\
-                     TMCNTSC_TCE)
+		     TMCNTSC_ALR |\
+		     TMCNTSC_TCF |\
+		     TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control         4-42
@@ -553,8 +553,8 @@
  * Periodic timer
  */
 #define CFG_PISCR   (PISCR_PS  |\
-                     PISCR_PTF |\
-                     PISCR_PTE)
+		     PISCR_PTF |\
+		     PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                           9-8
@@ -613,9 +613,9 @@
  *     - Valid
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
-                          BRx_PS_32                     |\
-                          BRx_MS_GPCM_P                 |\
-                          BRx_V)
+			  BRx_PS_32                     |\
+			  BRx_MS_GPCM_P                 |\
+			  BRx_V)
 
 /* OR0 is configured as follows:
  *
@@ -632,11 +632,11 @@
  *       current bank and the next access.
  */
 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE) |\
-                         ORxG_CSNT          |\
-                         ORxG_ACS_DIV1      |\
-                         ORxG_SCY_5_CLK     |\
-                         ORxG_TRLX          |\
-                         ORxG_EHTR)
+			 ORxG_CSNT          |\
+			 ORxG_ACS_DIV1      |\
+			 ORxG_SCY_5_CLK     |\
+			 ORxG_TRLX          |\
+			 ORxG_EHTR)
 
 /*-----------------------------------------------------------------------
  * BR2 - Base Register
@@ -668,9 +668,9 @@
  *     - Valid
  */
 #define CFG_BR2_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
-                          BRx_PS_64          |\
-                          BRx_MS_SDRAM_P     |\
-                          BRx_V)
+			  BRx_PS_64          |\
+			  BRx_MS_SDRAM_P     |\
+			  BRx_V)
 
 /* With a 16 MB DIMM, the OR2 is configured as follows:
  *
@@ -683,9 +683,9 @@
  */
 #if (CFG_SDRAM0_SIZE == 16)
 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
-                         ORxS_BPD_2         |\
-                         ORxS_ROWST_PBI0_A9 |\
-                         ORxS_NUMR_11)
+			 ORxS_BPD_2         |\
+			 ORxS_ROWST_PBI0_A9 |\
+			 ORxS_NUMR_11)
 
 /* With a 16 MB DIMM, the PSDMR is configured as follows:
  *
@@ -711,15 +711,15 @@
  *-----------------------------------------------------------------------
  */
 #define CFG_PSDMR   (PSDMR_RFEN       |\
-                     PSDMR_SDAM_A14_IS_A5 |\
-                     PSDMR_BSMA_A16_A18   |\
-                     PSDMR_SDA10_PBI0_A9  |\
-                     PSDMR_RFRC_7_CLK     |\
-                     PSDMR_PRETOACT_3W    |\
-                     PSDMR_ACTTORW_2W     |\
-                     PSDMR_LDOTOPRE_1C    |\
-                     PSDMR_WRC_1C         |\
-                     PSDMR_CL_2)
+		     PSDMR_SDAM_A14_IS_A5 |\
+		     PSDMR_BSMA_A16_A18   |\
+		     PSDMR_SDA10_PBI0_A9  |\
+		     PSDMR_RFRC_7_CLK     |\
+		     PSDMR_PRETOACT_3W    |\
+		     PSDMR_ACTTORW_2W     |\
+		     PSDMR_LDOTOPRE_1C    |\
+		     PSDMR_WRC_1C         |\
+		     PSDMR_CL_2)
 #endif /* (CFG_SDRAM0_SIZE == 16) */
 
 /* With a 64 MB DIMM, the OR2 is configured as follows:
@@ -733,9 +733,9 @@
  */
 #if (CFG_SDRAM0_SIZE == 64)
 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
-             ORxS_BPD_4         |\
-             ORxS_ROWST_PBI0_A8     |\
-             ORxS_NUMR_12)
+	     ORxS_BPD_4         |\
+	     ORxS_ROWST_PBI0_A8     |\
+	     ORxS_NUMR_12)
 
 /* With a 64 MB DIMM, the PSDMR is configured as follows:
  *
@@ -761,15 +761,15 @@
  *-----------------------------------------------------------------------
  */
 #define CFG_PSDMR   (PSDMR_RFEN       |\
-                     PSDMR_SDAM_A14_IS_A5 |\
-                     PSDMR_BSMA_A14_A16   |\
-                     PSDMR_SDA10_PBI0_A9  |\
-                     PSDMR_RFRC_7_CLK     |\
-                     PSDMR_PRETOACT_3W    |\
-                     PSDMR_ACTTORW_2W     |\
-                     PSDMR_LDOTOPRE_1C    |\
-                     PSDMR_WRC_1C         |\
-                     PSDMR_CL_2)
+		     PSDMR_SDAM_A14_IS_A5 |\
+		     PSDMR_BSMA_A14_A16   |\
+		     PSDMR_SDA10_PBI0_A9  |\
+		     PSDMR_RFRC_7_CLK     |\
+		     PSDMR_PRETOACT_3W    |\
+		     PSDMR_ACTTORW_2W     |\
+		     PSDMR_LDOTOPRE_1C    |\
+		     PSDMR_WRC_1C         |\
+		     PSDMR_CL_2)
 #endif  /* (CFG_SDRAM0_SIZE == 64) */
 
 #define CFG_PSRT    0x0e
@@ -800,13 +800,13 @@
 
 #ifdef CFG_IO_BASE
 #  define CFG_BR4_PRELIM  ((CFG_IO_BASE & BRx_BA_MSK)  |\
-                            BRx_PS_8                   |\
-                            BRx_MS_GPCM_L              |\
-                            BRx_V)
+			    BRx_PS_8                   |\
+			    BRx_MS_GPCM_L              |\
+			    BRx_V)
 
 #  define CFG_OR4_PRELIM   (ORxG_AM_MSK                |\
-                            ORxG_SCY_11_CLK            |\
-                            ORxG_EHTR)
+			    ORxG_SCY_11_CLK            |\
+			    ORxG_EHTR)
 #endif /* CFG_IO_BASE */
 
 /*
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 60699fe..cfe9032 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -113,7 +113,7 @@
 
 #define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
 
-                                                /* valid baudrates */
+						/* valid baudrates */
 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
@@ -175,7 +175,7 @@
  * JFFS2 Partitions
  */
 #define CFG_JFFS_CUSTOM_PART	1		/* see board/innokom/flash.c */
-#define CONFIG_MTD_INNOKOM_16MB 1		/* development flash         */	
+#define CONFIG_MTD_INNOKOM_16MB 1		/* development flash         */
 #undef  CONFIG_MTD_INNOKOM_64MB			/* production flash          */
 
 
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index cb737fc..2aee461 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -113,7 +113,7 @@
 
 #define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
 
-                                                /* valid baudrates */
+						/* valid baudrates */
 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
@@ -227,12 +227,12 @@
 
 #define CFG_GAFR0_L_VAL     (_BIT22+_BIT24+_BIT31)
 #define CFG_GAFR0_U_VAL     (_BIT15+_BIT17+_BIT19+\
-                             _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
+			     _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
 #define CFG_GAFR1_L_VAL     (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
-                             _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
+			     _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
 #define CFG_GAFR1_U_VAL     (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
 #define CFG_GAFR2_L_VAL     (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
-                             _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
+			     _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
 #define CFG_GAFR2_U_VAL     (_BIT1)
 
 #define CFG_PSSR_VAL        (0x20)
@@ -283,4 +283,3 @@
 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 
 #endif  /* __CONFIG_H */
-
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 95faa41..d71b3e9 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -211,16 +211,16 @@
 
 /* get the HRCW ISB field from CFG_IMMR */
 #define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
-                            ((CFG_IMMR & 0x01000000) >> 7)  |\
-                            ((CFG_IMMR & 0x00100000) >> 4) )
+			    ((CFG_IMMR & 0x01000000) >> 7)  |\
+			    ((CFG_IMMR & 0x00100000) >> 4) )
 
 #define CFG_HRCW_MASTER	(HRCW_L2CPC10 | \
 			 HRCW_DPPC11 | \
-                         CFG_RSD_HRCW_IMMR |\
-		     	 HRCW_MMR00 | \
-	     		 HRCW_APPC10 | \
-		     	 HRCW_CS10PC00 | \
-		     	 HRCW_MODCK_H0000 |\
+			 CFG_RSD_HRCW_IMMR |\
+			 HRCW_MMR00 | \
+			 HRCW_APPC10 | \
+			 HRCW_CS10PC00 | \
+			 HRCW_MODCK_H0000 |\
 			 CFG_RSD_HRCW_BOOT_FLAGS)
 
 /* no slaves */
@@ -388,9 +388,9 @@
 /* Virtex-FPGA - Register */
 #define CFG_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
 #define CFG_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
-                         ORxG_SCY_1_CLK | \
-                         ORxG_ACS_DIV2 | \
-                         ORxG_CSNT )
+			 ORxG_SCY_1_CLK | \
+			 ORxG_ACS_DIV2 | \
+			 ORxG_CSNT )
 
 /* local bus SDRAM */
 #define CFG_BR4_PRELIM	(PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 7accf74..6fd8abc 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -256,8 +256,8 @@
  */
 #define CONFIG_SOFT_SPI		/* Enable SPI driver */
 #define MAX_SPI_BYTES   4	/* Maximum number of bytes we can handle */
-#undef  DEBUG_SPI               /* Disable SPI debugging */  
- 
+#undef  DEBUG_SPI               /* Disable SPI debugging */
+
 /*
  * Software (bit-bang) SPI driver configuration
  */
@@ -273,9 +273,9 @@
 #undef  SPI_INIT			/* no port initialization needed */
 #define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
 #define SPI_SDA(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
-                        else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI
+			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI
 #define SPI_SCL(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
-                        else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK
+			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK
 #define SPI_DELAY                       /* No delay is needed */
 #endif /* CONFIG_SOFT_SPI */
 
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index d47c208..1822fbc 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -284,7 +284,7 @@
 /* What should the console's baud rate be? */
 #define CONFIG_BAUDRATE		9600
 
-/* Ethernet MAC address 
+/* Ethernet MAC address
  *     Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
  *           http://standards.ieee.org/regauth/oui/index.shtml
  */
@@ -315,38 +315,38 @@
 
 /* Define this to contain any number of null terminated strings that
  * will be part of the default enviroment compiled into the boot image.
- * 
+ *
  * Variable		Usage
  * --------------       -------------------------------------------------------
- * serverip		server IP address 
+ * serverip		server IP address
  * ipaddr		my IP address
  * reprog		Reload flash with a new copy of U-Boot
  * zapenv		Erase the environment area in flash
  * root-on-initrd       Set the bootcmd variable to allow booting of an initial
  *                      ram disk.
- * root-on-nfs          Set the bootcmd variable to allow booting of a NFS 
+ * root-on-nfs          Set the bootcmd variable to allow booting of a NFS
  *                      mounted root filesystem.
- * boot-hook            Convenient stub to do something useful before the 
+ * boot-hook            Convenient stub to do something useful before the
  *                      bootm command is executed.
- * 
+ *
  * Example usage of root-on-initrd and root-on-nfs :
  *
  * Note: The lines have been wrapped to improved its readability.
  *
  * => printenv bootcmd
  * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=$(serverip):$(rootpath) 
+ * nfsroot=$(serverip):$(rootpath)
  * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
  *
  * => run root-on-initrd
  * => printenv bootcmd
  * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
  * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
- * 
+ *
  * => run root-on-nfs
  * => printenv bootcmd
  * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=$(serverip):$(rootpath) 
+ * nfsroot=$(serverip):$(rootpath)
  * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
  *
  */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 292b4bf..764efdf 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -37,7 +37,7 @@
 #define CONFIG_SC520		1	/* Include support for AMD SC520 */
 #define CONFIG_ALI152X		1	/* Include support for Ali 152x SIO */
 
-#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */	
+#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
 #define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
 #define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
 
@@ -123,7 +123,7 @@
 #define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
 
 #define CONFIG_SPI_EEPROM      /* Support for SPI EEPROMs (AT25128) */
-#define CONFIG_MW_EEPROM       /* Support for MicroWire EEPROMs (AT93LC46) */ 
+#define CONFIG_MW_EEPROM       /* Support for MicroWire EEPROMs (AT93LC46) */
 
 
 /* allow to overwrite serial and ethaddr */
@@ -134,7 +134,7 @@
 #define CFG_ENV_IS_IN_EEPROM   1
 #define CONFIG_SPI
 #define CFG_ENV_SIZE	       0x4000	/* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/
-#define CFG_ENV_OFFSET         0      
+#define CFG_ENV_OFFSET         0
 #define CONFIG_SC520_CDP_USE_SPI  /* Store configuration in the SPI part */
 #undef CONFIG_SC520_CDP_USE_MW    /* Store configuration in the MicroWire part */
 #define CONFIG_SPI_X 1
@@ -157,7 +157,7 @@
 #define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
 #define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
-//#define CFG_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
+/*#define CFG_ATA_IDE1_OFFSET	0x0170	/###* ide1 offset */
 #define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
 #define CFG_ATA_REG_OFFSET	0	/* reg offset */
 #define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
@@ -187,7 +187,6 @@
 #define CFG_ISA_IO 0
 
 
-
 /************************************************************
  * RTC
  ***********************************************************/
@@ -202,9 +201,8 @@
 #define CONFIG_PCI_SCAN_SHOW
 
 #define	CFG_FIRST_PCI_IRQ   10
-#define	CFG_SECOND_PCI_IRQ  9 
-#define CFG_THIRD_PCI_IRQ   11 
+#define	CFG_SECOND_PCI_IRQ  9
+#define CFG_THIRD_PCI_IRQ   11
 #define	CFG_FORTH_PCI_IRQ   15
 
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index 0a28805..9d26beb 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -189,8 +189,6 @@
 #define CONFIG_ISO_PARTITION /* Experimental */
 
 
-
-
 /************************************************************
  * RTC
  ***********************************************************/
@@ -209,5 +207,4 @@
 #define	CFG_THIRD_PCI_IRQ   11
 #define	CFG_FORTH_PCI_IRQ   12
 
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_spunk_rel.h b/include/configs/sc520_spunk_rel.h
index 2d53530..2e7a7e1 100644
--- a/include/configs/sc520_spunk_rel.h
+++ b/include/configs/sc520_spunk_rel.h
@@ -27,6 +27,6 @@
 #include "sc520_spunk.h"
 
 #undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND	"fsload boot/vmlinuz ; bootm" 
+#define CONFIG_BOOTCOMMAND	"fsload boot/vmlinuz ; bootm"
 
 #endif
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index b46b0be..e9e86f6 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -92,22 +92,22 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
-        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-         "nfsroot=$(serverip):$(rootpath)\0"                     \
-        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-        "addip=setenv bootargs $(bootargs) "                            \
-               "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
-                ":$(hostname):$(netdev):off panic=1\0"                  \
-	        "flash_nfs=run nfsargs addip;"                                  \
-             "bootm $(kernel_addr)\0"                                \
-        "flash_self=run ramargs addip;"                                 \
-               "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
-        "net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0"     \
-        "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0"                                  \
-        "bootfile=pImage-sc855t\0"                           \
-        "kernel_addr=48000000\0"                                        \
-        "ramdisk_addr=48100000\0"                                       \
-        ""
+	"nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+	 "nfsroot=$(serverip):$(rootpath)\0"                     \
+	"ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+	"addip=setenv bootargs $(bootargs) "                            \
+	       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
+		":$(hostname):$(netdev):off panic=1\0"                  \
+		"flash_nfs=run nfsargs addip;"                                  \
+	     "bootm $(kernel_addr)\0"                                \
+	"flash_self=run ramargs addip;"                                 \
+	       "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
+	"net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0"     \
+	"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0"                                  \
+	"bootfile=pImage-sc855t\0"                           \
+	"kernel_addr=48000000\0"                                        \
+	"ramdisk_addr=48100000\0"                                       \
+	""
 #define CONFIG_BOOTCOMMAND							\
 	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
 	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
@@ -133,8 +133,8 @@
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-		                CFG_CMD_ASKENV  | \
-		 		CFG_CMD_DHCP	| \
+				CFG_CMD_ASKENV  | \
+				CFG_CMD_DHCP	| \
 				CFG_CMD_DOC	| \
 /*				CFG_CMD_IDE     |*/ \
 				CFG_CMD_DATE	)
@@ -272,7 +272,7 @@
  */
 #ifndef	CONFIG_CAN_DRIVER
 /*#define CFG_SIUMCR 0x00610c00	*/
-#define CFG_SIUMCR 0x00000000	
+#define CFG_SIUMCR 0x00000000
 #else	/* we must activate GPL5 in the SIUMCR for CAN */
 #define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 #endif	/* CONFIG_CAN_DRIVER */
@@ -309,16 +309,16 @@
 #elif defined (CONFIG_80MHz)
 #define CFG_PLPRCR 0x04f01000
 #define CONFIG_8xx_GCLK_FREQ 80000000
-#elif defined(CONFIG_75MHz)	
-#define CFG_PLPRCR 0x04a00100	
+#elif defined(CONFIG_75MHz)
+#define CFG_PLPRCR 0x04a00100
 #define CONFIG_8xx_GCLK_FREQ 75000000
-#elif defined(CONFIG_66MHz)	
-#define CFG_PLPRCR 0x04101000	
+#elif defined(CONFIG_66MHz)
+#define CFG_PLPRCR 0x04101000
 #define CONFIG_8xx_GCLK_FREQ 66000000
-#elif defined(CONFIG_50MHz)	
-#define CFG_PLPRCR 0x03101000	
+#elif defined(CONFIG_50MHz)
+#define CFG_PLPRCR 0x03101000
 #define CONFIG_8xx_GCLK_FREQ 50000000
-#endif	
+#endif
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -327,11 +327,11 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_BUS_DIV2	
+#ifdef	CONFIG_BUS_DIV2
 #define CFG_SCCR	0x02020000 | SCCR_RTSEL
 #else			/* up to 50 MHz we use a 1:1 clock */
 #define CFG_SCCR    0x02000000 | SCCR_RTSEL
-#endif	
+#endif
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
@@ -370,7 +370,7 @@
 					   */
 #define CFG_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
 					   */
-#define CONFIG_ATAPI    
+#define CONFIG_ATAPI
 #define CFG_PIO_MODE 0
 
 /*-----------------------------------------------------------------------
@@ -400,35 +400,35 @@
 /*
  * FLASH timing:
  */
-#if defined(CONFIG_100MHz) 
-#define CFG_OR_TIMING_FLASH 0x000002f4	
-#define CFG_OR_TIMING_DOC   0x000002f4	
+#if defined(CONFIG_100MHz)
+#define CFG_OR_TIMING_FLASH 0x000002f4
+#define CFG_OR_TIMING_DOC   0x000002f4
 #define CFG_MxMR_PTx 0x61000000
 #define CFG_MPTPR 0x400
 
 #elif  defined(CONFIG_80MHz)
-#define CFG_OR_TIMING_FLASH 0x00000ff4	
-#define CFG_OR_TIMING_DOC   0x000001f4	
+#define CFG_OR_TIMING_FLASH 0x00000ff4
+#define CFG_OR_TIMING_DOC   0x000001f4
 #define CFG_MxMR_PTx 0x4e000000
 #define CFG_MPTPR 0x400
 
-#elif defined(CONFIG_75MHz) 
-#define CFG_OR_TIMING_FLASH 0x000008f4	
-#define CFG_OR_TIMING_DOC   0x000002f4	
+#elif defined(CONFIG_75MHz)
+#define CFG_OR_TIMING_FLASH 0x000008f4
+#define CFG_OR_TIMING_DOC   0x000002f4
 #define CFG_MxMR_PTx 0x49000000
 #define CFG_MPTPR 0x400
 
 #elif defined(CONFIG_66MHz)
 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-        OR_SCY_3_CLK | OR_EHTR | OR_BI)
+	OR_SCY_3_CLK | OR_EHTR | OR_BI)
 /*#define CFG_OR_TIMING_FLASH 0x000001f4 */
-#define CFG_OR_TIMING_DOC   0x000003f4	
+#define CFG_OR_TIMING_DOC   0x000003f4
 #define CFG_MxMR_PTx  0x40000000
 #define CFG_MPTPR 0x400
 
 #else		/*   50 MHz */
 #define CFG_OR_TIMING_FLASH 0x00000ff4
-#define CFG_OR_TIMING_DOC   0x000001f4	
+#define CFG_OR_TIMING_DOC   0x000001f4
 #define CFG_MxMR_PTx  0x30000000
 #define CFG_MPTPR 0x400
 #endif	/*CONFIG_??MHz */
diff --git a/include/configs/v37.h b/include/configs/v37.h
index f527440..6696985 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -376,6 +376,4 @@
 #define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index c88c4ab..ecb7215 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * Copyright (C) 2003 ETC s.r.o.
  *
  * This program is free software; you can redistribute it and/or
@@ -52,7 +52,7 @@
 /*
  * Boot options. Setting delay to -1 stops autostart count down.
  * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept 
+ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
  * parameters at all! Do not get confused by them so.
  */
 #define CONFIG_BOOTDELAY   -1
@@ -71,7 +71,7 @@
 #define CFG_BARGSIZE            CFG_CBSIZE            /* boot args buf size  */
 
 #define CFG_MEMTEST_START       0xa0400000            /* memtest test area   */
-#define CFG_MEMTEST_END         0xa0800000      
+#define CFG_MEMTEST_END         0xa0800000
 
 #undef  CFG_CLKS_IN_HZ                       /* use HZ for freq. display     */
 
@@ -128,7 +128,7 @@
 #define CFG_MAX_FLASH_BANKS    	1  	/* FLASH banks count (not chip count)*/
 #define CFG_MAX_FLASH_SECT     	128	/* number of sector in FLASH bank    */
 #define WEP_FLASH_BUS_WIDTH 	4	/* we use 32 bit FLASH memory...     */
-#define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */ 
+#define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */
 #define WEP_FLASH_BANK_SIZE  0x2000000  /* size of one flash bank*/
 #define WEP_FLASH_SECT_SIZE  0x0040000  /* size of erase sector */
 #define WEP_FLASH_BASE       0x0000000  /* location of flash memory */
@@ -137,9 +137,9 @@
 
 /* This should be defined if CFI FLASH device is present. Actually benefit
    is not so clear to me. In other words we can provide more informations
-   to user, but this expects more complex flash handling we do not provide 
+   to user, but this expects more complex flash handling we do not provide
    now.*/
-#undef  CFG_FLASH_CFI	
+#undef  CFG_FLASH_CFI
 
 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ)    /* timeout for Erase operation */
 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ)    /* timeout for Write operation */
@@ -173,7 +173,7 @@
 #define CFG_MONITOR_LEN		0x20000		/* 128kb ( 1 flash sector )  */
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR		0x20000	        /* absolute address for now  */
-#define CFG_ENV_SIZE		0x2000	        
+#define CFG_ENV_SIZE		0x2000
 
 #undef  CONFIG_ENV_OVERWRITE                    /* env is not writable now   */
 
@@ -185,4 +185,3 @@
 #define CFG_LOAD_ADDR        0x40000
 
 #endif  /* __CONFIG_H */
-