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| author | Jason Jin <Jason.jin@freescale.com> | 2008-09-27 14:40:57 +0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-10-07 15:37:08 -0500 |
| commit | c0391111c33c22fabeddf8f4ca801ec7645b4f5c (patch) | |
| tree | 38f34ae2b3cdb04300ee0c5afb08e9317c2e5d05 /include/configs | |
| parent | bac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4 (diff) | |
| download | u-boot-imx-c0391111c33c22fabeddf8f4ca801ec7645b4f5c.zip u-boot-imx-c0391111c33c22fabeddf8f4ca801ec7645b4f5c.tar.gz u-boot-imx-c0391111c33c22fabeddf8f4ca801ec7645b4f5c.tar.bz2 | |
Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8536DS.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 2578bef..0d65b20 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -59,7 +59,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq from ICS307 instead of switches */ |