diff options
| author | wdenk <wdenk> | 2004-06-10 21:34:36 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-06-10 21:34:36 +0000 |
| commit | b54d32b40d95d399dd1f53f24c93b0cf5c42460d (patch) | |
| tree | dba569eef315497f378c460e0e72ce98df053dd1 /include/configs | |
| parent | 681334540d109558fe7c382faf9c705439c2dfa3 (diff) | |
| download | u-boot-imx-b54d32b40d95d399dd1f53f24c93b0cf5c42460d.zip u-boot-imx-b54d32b40d95d399dd1f53f24c93b0cf5c42460d.tar.gz u-boot-imx-b54d32b40d95d399dd1f53f24c93b0cf5c42460d.tar.bz2 | |
* Patch by Robert Schwebel, 10 Jun 2004:
Add support for Intel K3 strata flash.
* Some cleanup
* Patch by Thomas Brand, 10 Jun 2004:
Fix "loads" command on DK1S10 board
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/DK1S10.h | 1 | ||||
| -rw-r--r-- | include/configs/FADS823.h | 3 | ||||
| -rw-r--r-- | include/configs/FADS850SAR.h | 3 |
3 files changed, 5 insertions, 2 deletions
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index b2e86c8..e79eb49 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -142,6 +142,7 @@ #if (CFG_NIOS_CPU_UART_NUMS != 0) #define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #if (CFG_NIOS_CPU_UART0_BR != 0) #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 4f3d397..726ab37 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -366,8 +366,9 @@ #define BCSR1_PCCVCC1 ((uint)0x00010000) #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_FLASH_PD_SHIFT 28 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) +#define BCSR2_DRAM_PD_SHIFT 23 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000) #define BCSR2_DBREVNR_MASK ((uint)0x00030000) diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index 9e292ae..2a986f0 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -333,8 +333,9 @@ #define BCSR1_PCCVCC1 ((uint)0x00010000) #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_FLASH_PD_SHIFT 28 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) +#define BCSR2_DRAM_PD_SHIFT 23 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000) #define BCSR2_DBREVNR_MASK ((uint)0x00030000) |