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| author | wdenk <wdenk> | 2004-11-17 20:44:20 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-11-17 20:44:20 +0000 |
| commit | cacfab588a897c369a4906818c5ed4bc40a450c5 (patch) | |
| tree | 7fbfe9859cd50211f3089070b145474ac7db0cbd /include/configs | |
| parent | 1f6d4258c25bc41ce8404d3485ace1989f796a2f (diff) | |
| download | u-boot-imx-cacfab588a897c369a4906818c5ed4bc40a450c5.zip u-boot-imx-cacfab588a897c369a4906818c5ed4bc40a450c5.tar.gz u-boot-imx-cacfab588a897c369a4906818c5ed4bc40a450c5.tar.bz2 | |
Map SRAM on NC650 board
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/NC650.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 8f52014..c62d879 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -335,6 +335,21 @@ #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) /* + * BR5 and OR5 (SRAM) + */ +#define CFG_SRAM_BASE 0x60000000 +#define CFG_SRAM_SIZE 0x00080000 + +#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_15_CLK | OR_EHTR | OR_TRLX) + +#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM) + + + + +/* * 4096 Rows from SDRAM example configuration * 1000 factor s -> ms * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration |