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| author | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
| commit | 1a247ba7fa5fb09f56892a09a990f03ce564b3e2 (patch) | |
| tree | 9dab0ef013cc6dc7883454808ecf6ba4d7a7a94e /include/configs | |
| parent | 2c289e320dcfb3760e99cf1d765cb067194a1202 (diff) | |
| parent | 8155efbd7ae9c65564ca98affe94631d612ae088 (diff) | |
| download | u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.zip u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.tar.gz u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.tar.bz2 | |
Merge commit 'wd/master'
Diffstat (limited to 'include/configs')
231 files changed, 2711 insertions, 1079 deletions
diff --git a/include/configs/A3000.h b/include/configs/A3000.h index 0a9a1ff..dba1bf7 100644 --- a/include/configs/A3000.h +++ b/include/configs/A3000.h @@ -87,7 +87,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -95,9 +95,9 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ #define CONFIG_NET_MULTI /* Multi ethernet cards support */ @@ -120,11 +120,11 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ +#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the @@ -170,7 +170,7 @@ * Definitions for initial stack pointer and data area */ -/* #define CFG_MONITOR_BASE TEXT_BASE */ +/* #define CFG_MONITOR_BASE TEXT_BASE */ /*#define CFG_GBL_DATA_SIZE 256*/ #define CFG_GBL_DATA_SIZE 128 #define CFG_INIT_RAM_ADDR 0x40000000 @@ -192,7 +192,7 @@ */ #define CFG_ROMNAL 7 #define CFG_ROMFAL 11 -#define CFG_DBUS_SIZE 0x3 +#define CFG_DBUS_SIZE 0x3 /* Bit-field values for MCCR2. */ @@ -218,7 +218,7 @@ #define CFG_EXTROM 1 #define CFG_REGDIMM 0 -#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ +#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index c45c395..01ee72b 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -81,9 +81,9 @@ * appropriately -- this is very important if you plan to move your * memory to another place as configured at this time !!!). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h index 55210eb..c8428b4 100644 --- a/include/configs/ADNPESC1_base_32.h +++ b/include/configs/ADNPESC1_base_32.h @@ -370,10 +370,10 @@ #define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */ #define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ +#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ #define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */ -#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ +#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ /* memory accessibility */ #undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h index 6f64038..035ebc6 100644 --- a/include/configs/AMX860.h +++ b/include/configs/AMX860.h @@ -115,7 +115,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 8ad33f1..02f0c76 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -36,7 +36,7 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_APCG405 1 /* ...on a APC405 board */ +#define CONFIG_APCG405 1 /* ...on a APC405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_BOARD_EARLY_INIT_R 1 diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 50f09b0..0602381 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -208,7 +208,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/ #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ +#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ #define CFG_ENV_ADDR_REDUND 0xFFFA0000 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 0d644da..f05c1d5 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -55,7 +55,7 @@ #define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -84,7 +84,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ +#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ #define CONFIG_ENABLE_36BIT_PHYS 1 #undef CFG_DRAM_TEST #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ @@ -276,7 +276,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #if defined(CONFIG_PCI) diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 8a76c26..7389c38 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -149,7 +149,7 @@ /* Environment is in flash */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CONFIG_ENV_OVERWRITE @@ -191,16 +191,16 @@ #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) /* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CFG_PISCR (PISCR_PS | PISCR_PITF) /* PLPRCR - PLL, Low-Power, and Reset Control Register */ -/* #define CFG_PLPRCR PLPRCR_TEXPS */ +/* #define CFG_PLPRCR PLPRCR_TEXPS */ /* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 +#define SCCR_MASK SCCR_EBDF11 #define CFG_SCCR SCCR_RTSEL -#define CFG_DER 0 +#define CFG_DER 0 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 3f2f614..38b962f 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_ALASKA8220 1 /* ... on Alaska board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/B2.h b/include/configs/B2.h index f1411db..d6ab1ad 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -37,7 +37,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_B2 1 /* on an B2 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 706c13e..b7574bf 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -61,6 +61,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 9f06957..6194c5c 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -137,7 +137,7 @@ #define CFG_LOAD_ADDR 0x00100000 /* default load address */ /* Ethernet hardware configuration done using port pins */ -#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ +#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ #define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ #define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ #define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 48e29a2..89edbde 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -61,6 +61,8 @@ #undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* which initialization functions to call for this board */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 9763e64..10cebc9 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -115,9 +115,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /*----------------------------------------------------------------------- diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 2356858..604779a 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -130,16 +130,16 @@ /* * Miscellaneous configurable options */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */ +#define CFG_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */ #define CFG_TFTP_LOADADDR CFG_LOAD_ADDR -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_DRAM_TEST 1 /*----------------------------------------------------------------------- @@ -218,7 +218,7 @@ #else #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) diff --git a/include/configs/CU824.h b/include/configs/CU824.h index 8b50087..f36d8da 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -305,7 +305,7 @@ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_TULIP #define CONFIG_TULIP_USE_IO diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index eb78080..fb06689 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -76,9 +76,9 @@ * a memory resource (so you must make sure TEXT_BASE is chosen * appropriately). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index bd36071..7a9ef79 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -84,9 +84,9 @@ * a memory resource (so you must make sure TEXT_BASE is chosen * appropriately). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h index 4eb9629..0115699 100644 --- a/include/configs/DK1S10_mtx_ldk_20.h +++ b/include/configs/DK1S10_mtx_ldk_20.h @@ -147,7 +147,7 @@ /* IDE i/f */ #define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ #define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ /* memory accessibility */ #undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ diff --git a/include/configs/DU440.h b/include/configs/DU440.h index d54da97..0f5f85c 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -375,11 +375,11 @@ int du440_phy_addr(int devnum); #define CFG_FLASH CFG_FLASH_BASE #define CFG_CPLD_BASE 0xC0000000 -#define CFG_CPLD_RANGE 0x00000010 +#define CFG_CPLD_RANGE 0x00000010 #define CFG_DUMEM_BASE 0xC0100000 -#define CFG_DUMEM_RANGE 0x00100000 +#define CFG_DUMEM_RANGE 0x00100000 #define CFG_DUIO_BASE 0xC0200000 -#define CFG_DUIO_RANGE 0x00010000 +#define CFG_DUIO_RANGE 0x00010000 #define CFG_NAND0_CS 2 /* NAND chip connected to CSx */ #define CFG_NAND1_CS 3 /* NAND chip connected to CSx */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index 5ba7585..417099e 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -95,7 +95,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL @@ -157,7 +157,7 @@ */ #define CFG_INIT_RAM_ADDR 0x20000000 #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -219,13 +219,13 @@ #define CFG_CS0_BASE CFG_FLASH_BASE #define CFG_CS0_SIZE 2*1024*1024 #define CFG_CS0_WIDTH 16 -#define CFG_CS0_RO 0 +#define CFG_CS0_RO 0 #define CFG_CS0_WS 6 #define CFG_CS3_BASE 0xE0000000 #define CFG_CS3_SIZE 1*1024*1024 #define CFG_CS3_WIDTH 16 -#define CFG_CS3_RO 0 +#define CFG_CS3_RO 0 #define CFG_CS3_WS 6 /*----------------------------------------------------------------------- @@ -250,7 +250,7 @@ #define CFG_PEHLPAR 0xC0 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ #define CFG_DDRUA 0x05 -#define CFG_PJPAR 0xFF; +#define CFG_PJPAR 0xFF; /*----------------------------------------------------------------------- * CCM configuration diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h index c2ab18a..7824b90 100644 --- a/include/configs/EP88x.h +++ b/include/configs/EP88x.h @@ -144,7 +144,7 @@ /* Environment is in flash */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_OR0_PRELIM 0xFC000160 @@ -192,13 +192,13 @@ #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) /* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR PISCR_PS +#define CFG_PISCR PISCR_PS /* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 +#define SCCR_MASK SCCR_EBDF11 #define CFG_SCCR SCCR_RTSEL -#define CFG_DER 0 +#define CFG_DER 0 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index dc15b0c..bfdcf6a 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -330,7 +330,7 @@ * BR0/1 and OR0/1 (FLASH) */ -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h index ed439b1..525051f 100644 --- a/include/configs/ETX094.h +++ b/include/configs/ETX094.h @@ -51,7 +51,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ -#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ +#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ #define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ #define CONFIG_ETHADDR 08:00:06:00:00:00 diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index 1c44a0c..c9d8c27 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -42,7 +42,7 @@ #define CONFIG_EVB64260 1 /* this is an EVB64260 board */ #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ #undef CONFIG_ECC /* enable ECC support */ /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ @@ -91,7 +91,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp && " \ + "bootp && " \ "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:" \ "$netmask:$hostname:eth0:none; && " \ @@ -412,10 +412,10 @@ #define CFG_L2 #ifdef CONFIG_750CX -#define L2_INIT 0 +#define L2_INIT 0 #else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #endif #define L2_ENABLE (L2_INIT | L2CR_L2E) diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index 251227c..99d1cf2 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 86cbe58..6f3e6a7 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -93,10 +93,10 @@ #define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ #define CONFIG_BOOTARGS "" #define CONFIG_BOOTCOMMAND \ -"bootp ;" \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ +"bootp ;" \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ "bootm" #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index c8b5a6d..037b115 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -39,9 +39,9 @@ * Identify the board */ #if !defined(CONFIG_SC) -#define CONFIG_IDENT_STRING " B2" +#define CONFIG_IDENT_STRING " B2" #else -#define CONFIG_IDENT_STRING " SC" +#define CONFIG_IDENT_STRING " SC" #endif /* @@ -50,26 +50,26 @@ * generated by the DS1337 - and the DS1337 clock can be turned off. */ #if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 +#define CONFIG_8xx_GCLK_FREQ 66600000 #else -#define CONFIG_8xx_GCLK_FREQ 48000000 +#define CONFIG_8xx_GCLK_FREQ 48000000 #endif /* * The RS-232 console port is on SMC1 */ #define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 /* * Set allowable console baud rates */ -#define CFG_BAUDRATE_TABLE { 9600, \ - 19200, \ - 38400, \ - 57600, \ - 115200, \ - } +#define CFG_BAUDRATE_TABLE { 9600, \ + 19200, \ + 38400, \ + 57600, \ + 115200, \ + } /* * Print console information @@ -148,7 +148,7 @@ #define CFG_DISCOVER_PHY #define CONFIG_MII #define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_ADDR 0 /* * Set default IP stuff just to get bootstrap entries into the @@ -172,7 +172,7 @@ * Enable I2C and select the hardware/software driver */ #define CONFIG_HARD_I2C 1 /* CPM based I2C */ -#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ +#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ #ifdef CONFIG_HARD_I2C #define CFG_I2C_SPEED 100000 /* clock speed in Hz */ @@ -181,7 +181,7 @@ #ifdef CONFIG_SOFT_I2C #define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ +#define PB_SDA 0x00000010 /* PB 27 */ #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) @@ -388,7 +388,7 @@ */ #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ +#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -480,18 +480,18 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ + SYPCR_SWE | \ SYPCR_SWRI | \ SYPCR_SWP \ ) #else #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ SYPCR_SWP \ ) #endif @@ -557,18 +557,18 @@ #define SCCR_MASK SCCR_EBDF11 #if !defined(CONFIG_SC) -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ SCCR_DFNL000 | \ SCCR_DFNH000 \ ) #else -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ SCCR_DFNL000 | \ SCCR_DFNH000 | \ SCCR_RTDIV | \ @@ -614,7 +614,7 @@ #define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ BR_MS_GPCM | \ BR_PS_8 | \ - BR_V \ + BR_V \ ) /* @@ -626,9 +626,9 @@ ) #define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ + BR_MS_UPMA | \ + BR_PS_32 | \ + BR_V \ ) /* @@ -646,9 +646,9 @@ * MAMR settings for SDRAM */ #define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ + MAMR_PTAE | \ MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ + MAMR_DSA_1_CYCL | \ MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | \ MAMR_WLFA_1X | \ @@ -660,7 +660,7 @@ * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, * no burst. */ -#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_CSNT_SAM | \ OR_ACS_DIV2 | \ OR_BI | \ @@ -685,20 +685,20 @@ */ #define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ OR_SCY_15_CLK | \ - OR_BI \ + OR_BI \ ) #define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ BR_PS_32 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* * CS4* configuration for FPGA SelectMap configuration interface. * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge * of GCLK1_50 */ -#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_G5LS | \ OR_BI \ ) @@ -706,7 +706,7 @@ #define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ BR_PS_8 | \ BR_MS_UPMB | \ - BR_V \ + BR_V \ ) /* @@ -728,7 +728,7 @@ #define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ BR_PS_16 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* @@ -760,5 +760,3 @@ #endif #endif /* __CONFIG_GEN860T_H */ - -/* vim: set ts=4 tw=78 ai shiftwidth=4: */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h index 3a660ed..f6d6ae0 100644 --- a/include/configs/GENIETV.h +++ b/include/configs/GENIETV.h @@ -80,10 +80,10 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 9600 -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 5000000 /* 4 MHz clock */ +#define MPC8XX_FACT 12 /* Multiply by 12 */ +#define MPC8XX_XIN 5000000 /* 4 MHz clock */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) #define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ @@ -95,9 +95,9 @@ #define CONFIG_BOOTARGS "" #define CONFIG_BOOTCOMMAND \ "bootp; tftp; " \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ "bootm " #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ @@ -197,7 +197,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ /* values according to the manual */ @@ -291,15 +291,15 @@ #define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ /* FLASH timing */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ OR_SCY_15_CLK | OR_TRLX ) /*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */ -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ /* diff --git a/include/configs/GTH.h b/include/configs/GTH.h index 79f5714..00e09f7 100644 --- a/include/configs/GTH.h +++ b/include/configs/GTH.h @@ -135,7 +135,7 @@ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ /* Default location to load data from net */ -#define CFG_LOAD_ADDR 0x100000 +#define CFG_LOAD_ADDR 0x100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -196,7 +196,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #undef CFG_ENV_IS_IN_EEPROM #define CFG_ENV_OFFSET 0x000E0000 -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 18e5b3c..8ea1ac3 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -41,7 +41,7 @@ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_HH405 1 /* ...on a HH405 board */ +#define CONFIG_HH405 1 /* ...on a HH405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h index 7f3f16d..87827ea 100644 --- a/include/configs/IAD210.h +++ b/include/configs/IAD210.h @@ -70,15 +70,15 @@ #undef CONFIG_BOOTARGS /* #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" */ #define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs" \ - "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ + "setenv bootargs root=/dev/nfs" \ + "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -159,7 +159,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index 9c88d7c..f693956 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -72,9 +72,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -164,7 +164,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h index bb2c96a..7d564a0 100644 --- a/include/configs/IPHASE4539.h +++ b/include/configs/IPHASE4539.h @@ -274,7 +274,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) + HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 965b515..760f7cc 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -186,7 +186,7 @@ /* Environment is in flash, there is little space left in Serial EEPROM */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index 1142f2a..0ffdfac 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -205,7 +205,7 @@ # if defined (CONFIG_IVML24_16M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) # elif defined (CONFIG_IVML24_32M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWP) @@ -265,7 +265,7 @@ /* 0x01800014 */ #define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD101 | \ @@ -458,8 +458,8 @@ #if defined (CONFIG_IVML24_16M) /* 8 column SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) #elif defined (CONFIG_IVML24_32M) /* 128 MBit SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index bd19dad..ea3ffe0 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -200,7 +200,7 @@ #if defined(CONFIG_WATCHDOG) # if defined (CONFIG_IVMS8_16M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) # elif defined (CONFIG_IVMS8_32M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWP) @@ -259,7 +259,7 @@ /* 0x01800014 */ #define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD101 | \ @@ -440,8 +440,8 @@ #if defined (CONFIG_IVMS8_16M) /* 8 column SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) #elif defined (CONFIG_IVMS8_32M) /* 128 MBit SDRAM */ #define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 38a0226..3a347ea 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ @@ -172,9 +174,9 @@ * IPB Bus clocking configuration. */ #if defined(CONFIG_LITE5200B) -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #else -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif #endif /* CONFIG_MPC5200 */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 3ee2b39..8af1c52 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -84,7 +84,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index e1cc720..a6fac4c 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -95,7 +95,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 2b8734b..7edd322 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -97,7 +97,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 826778c..df46ee4 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -82,7 +82,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL @@ -215,13 +215,13 @@ #define CFG_CS0_BASE CFG_FLASH_BASE #define CFG_CS0_SIZE 2*1024*1024 #define CFG_CS0_WIDTH 16 -#define CFG_CS0_RO 0 +#define CFG_CS0_RO 0 #define CFG_CS0_WS 6 /* #define CFG_CS3_BASE 0xE0000000 #define CFG_CS3_SIZE 1*1024*1024 #define CFG_CS3_WIDTH 16 -#define CFG_CS3_RO 0 +#define CFG_CS3_RO 0 #define CFG_CS3_WS 6 */ /*----------------------------------------------------------------------- @@ -246,6 +246,6 @@ #define CFG_PEHLPAR 0xC0 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ #define CFG_DDRUA 0x05 -#define CFG_PJPAR 0xFF; +#define CFG_PJPAR 0xFF; #endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 42692d6..b30d99c 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -77,7 +77,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 3b9da17..a710c6d 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -77,7 +77,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index fea7551..a19c342 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -83,7 +83,7 @@ # define CFG_FEC1_PINMUX 0 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 454d0a2..b73e2e0 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -83,7 +83,7 @@ # define CFG_FEC1_PINMUX 0 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 9ddf82b..d683b87 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -123,7 +123,7 @@ * (to get SDRAM settings) ***************************************************************/ /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 -#define SDRAM_EEPROM_READ_ADDRESS 0xA1 +#define SDRAM_EEPROM_READ_ADDRESS 0xA1 */ /************************************************************** * Environment definitions @@ -132,7 +132,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ @@ -260,7 +260,7 @@ /*----------------------------------------------------------------------- * Logbuffer Configuration */ -#undef CONFIG_LOGBUFFER /* supported but not enabled */ +#undef CONFIG_LOGBUFFER /* supported but not enabled */ /*----------------------------------------------------------------------- * Bootcountlimit Configuration */ @@ -271,8 +271,8 @@ */ #if 0 /* enable this if POST is desired (is supported but not enabled) */ #define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_RTC | \ + CFG_POST_CPU | \ + CFG_POST_RTC | \ CFG_POST_I2C) #endif @@ -292,7 +292,7 @@ #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 -#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 +#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 /*----------------------------------------------------------------------- @@ -301,7 +301,7 @@ #define CFG_TEMP_STACK_OCM 1 #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -362,7 +362,7 @@ #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h index 9370c24..021729b 100644 --- a/include/configs/MOUSSE.h +++ b/include/configs/MOUSSE.h @@ -265,18 +265,18 @@ #else #define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) #endif -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT1L CFG_IBAT1L /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ -#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) +#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) #define CFG_DBAT2U CFG_IBAT2U #define CFG_DBAT2L CFG_IBAT2L /* PCI Memory region 2: PCI Devices in 0xFD space */ -#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) #define CFG_DBAT3U CFG_IBAT3U #define CFG_DBAT3L CFG_IBAT3L @@ -299,7 +299,7 @@ #if 0 #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ +#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ #else #define CFG_ENV_IS_IN_NVRAM 1 @@ -339,7 +339,7 @@ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_TULIP diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 6eec240..d547681 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -42,9 +42,12 @@ /* * On-board devices + * + * TSEC1 is VSC switch + * TSEC2 is SoC TSEC */ #define CONFIG_VSC7385_ENET - +#define CONFIG_TSEC2 #ifdef CFG_66MHZ #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ @@ -80,7 +83,7 @@ #ifdef CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 +#define CONFIG_TSEC1 /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 @@ -209,12 +212,12 @@ /* * Local Bus LCRR and LBCR regs */ -#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ +#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ -#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ /* drivers/mtd/nand/nand.c */ #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ @@ -466,6 +469,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -523,13 +528,8 @@ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:95:01 -#endif - -#ifdef CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 -#endif #define CONFIG_IPADDR 10.0.0.2 #define CONFIG_SERVERIP 10.0.0.1 @@ -551,28 +551,28 @@ #define MK_STR(x) XMK_STR(x) #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "ethprime=TSEC1\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "console=ttyS0\0" \ "setbootargs=setenv bootargs " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ - "run setbootargs;" \ - "run setipargs;" \ + "run setbootargs;" \ + "run setipargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index e0a887c..7a5d0aa 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -453,6 +453,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 32f57ac..977c041 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -468,6 +468,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index ddefa5e..9ca2a2b 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -483,6 +483,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -574,7 +576,7 @@ #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index cf552c2..bd77540 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -39,7 +39,7 @@ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ #undef CONFIG_PCI -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #define PCI_66M #ifdef PCI_66M @@ -414,7 +414,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xFIXME #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -626,6 +626,7 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index be8850a..38410a1 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -149,8 +149,8 @@ * DDR Setup */ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_83XX_DDR_USES_CS0 #define CFG_MEMTEST_START 0x1000 /* memtest region */ #define CFG_MEMTEST_END 0x2000 @@ -187,7 +187,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_FLASH_QUIET_TEST #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ @@ -555,6 +555,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -671,21 +672,21 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=" MK_STR(CONFIG_CONSOLE) "\0" \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "console=" MK_STR(CONFIG_CONSOLE) "\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 983575e..fcfbe6f 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -515,6 +515,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f6af6..adedcb9 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -419,6 +419,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -535,11 +537,11 @@ "ubootfile=u-boot.bin\0"\ "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ - "$mtdparts panic=1\0"\ + "$mtdparts panic=1\0"\ "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ - "$gatewayip:$netmask:$hostname:$netdev:off "\ - "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ + "$gatewayip:$netmask:$hostname:$netdev:off "\ + "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\ "rootfstype=jffs2 rw\0"\ "tftp_get_uboot=tftp 100000 $ubootfile\0"\ @@ -555,7 +557,7 @@ "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\ "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\ "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ - "cp.b 100000 ff800000 $filesize\0"\ + "cp.b 100000 ff800000 $filesize\0"\ "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\ "nand_write_kernel\0"\ "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e92493a..4e159a0 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -502,6 +502,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f7e6fd2..29c2490 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -524,6 +524,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 85934d7..5719759 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -46,7 +46,7 @@ #endif #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -98,7 +98,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -147,7 +147,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -268,16 +268,16 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -337,7 +337,7 @@ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -345,7 +345,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -357,7 +357,7 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 77eea73..b13c81c 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -30,14 +30,14 @@ #ifndef __CONFIG_H #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_MPC8540 1 /* MPC8540 specific */ #define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI /* pci ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -63,7 +63,7 @@ #endif /* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #undef CONFIG_BTB /* toggle branch predition */ #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -81,8 +81,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -113,7 +113,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ #define CFG_FLASH_CFI 1 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -150,16 +150,16 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -168,7 +168,7 @@ #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -203,17 +203,17 @@ #define CONFIG_NET_MULTI #undef CONFIG_EEPRO100 #define CONFIG_TULIP -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 -#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ #endif #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #define CFG_PCI_SUBSYS_DEVICEID 0x0008 #elif defined(CONFIG_TSEC_ENET) -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_HAS_ETH0 @@ -262,7 +262,7 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ +#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -318,7 +318,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* * Internal Definitions diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 3f3f741..5b3ea05 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -38,7 +38,7 @@ #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void); #define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -362,7 +362,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* * Internal Definitions diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 500b57c..e838345 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -38,7 +38,7 @@ #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void); #define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -361,7 +361,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 @@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* * Internal Definitions diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index e30302c..9c95cc6 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -42,7 +42,7 @@ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -93,7 +93,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -142,7 +142,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -263,23 +263,23 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -325,7 +325,7 @@ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -333,7 +333,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -345,7 +345,7 @@ #ifdef CONFIG_TSEC_ENET #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #ifndef CONFIG_MII @@ -367,9 +367,9 @@ #endif /* CONFIG_TSEC_ENET */ -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ +#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ #if (CONFIG_ETHER_INDEX == 2) @@ -387,7 +387,7 @@ #elif (CONFIG_ETHER_INDEX == 3) /* need more definitions here for FE3 */ #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ +#endif /* CONFIG_ETHER_INDEX */ #ifndef CONFIG_MII #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 7bb20e5..a7c69d2 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -38,7 +38,7 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -68,7 +68,7 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -88,7 +88,7 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -166,7 +166,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -184,10 +184,10 @@ extern unsigned long get_clock_freq(void); #define CFG_BR2_PRELIM 0xf0001861 #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * LSDMR masks @@ -267,16 +267,16 @@ extern unsigned long get_clock_freq(void); #define CFG_OR5_PRELIM 0xffff69f7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -350,7 +350,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_eTSEC_MDIO_BUS #ifdef CONFIG_eTSEC_MDIO_BUS -#define CONFIG_MIIM_ADDRESS 0xE0024520 +#define CONFIG_MIIM_ADDRESS 0xE0024520 #endif #define CONFIG_UEC_ETH1 /* GETH1 */ @@ -379,7 +379,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -395,7 +395,7 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #if defined(CONFIG_TSEC_ENET) @@ -480,7 +480,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* * Internal Definitions diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index ed75357..fc16890 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -55,6 +55,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ #define CONFIG_ALTIVEC 1 /* @@ -328,7 +329,7 @@ #define CONFIG_USB_KEYBOARD 1 #define CFG_DEVICE_DEREGISTER #define CFG_USB_EVENT_POLL 1 -#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #define CFG_OHCI_SWAP_REG_ACCESS 1 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d7a7f90..455e154 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -36,11 +36,11 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #ifdef RUN_DIAG -#define CFG_DIAG_ADDR 0xff800000 +#define CFG_DIAG_ADDR 0xff800000 #endif #define CFG_RESET_ADDRESS 0xfff00100 @@ -51,7 +51,7 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -61,14 +61,15 @@ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_NUM_DDR_CONTROLLERS 2 -/* #define CONFIG_DDR_INTERLEAVE 1 */ +/* #define CONFIG_DDR_INTERLEAVE 1 */ #define CACHE_LINE_INTERLEAVING 0x20000000 #define PAGE_INTERLEAVING 0x21000000 #define BANK_INTERLEAVING 0x22000000 #define SUPER_BANK_INTERLEAVING 0x23000000 +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ -#define CONFIG_ALTIVEC 1 +#define CONFIG_ALTIVEC 1 /* * L2CR setup -- make sure this is right for your board! @@ -81,7 +82,7 @@ #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ @@ -93,7 +94,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -126,18 +127,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ #define CFG_DDR_CS0_BNDS 0x0000000F - #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ #define CFG_DDR_EXT_REFRESH 0x00000000 - #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_0 0x00260802 #define CFG_DDR_TIMING_1 0x39357322 #define CFG_DDR_TIMING_2 0x14904cc8 #define CFG_DDR_MODE_1 0x00480432 #define CFG_DDR_MODE_2 0x00000000 #define CFG_DDR_INTERVAL 0x06090100 - #define CFG_DDR_DATA_INIT 0xdeadbeef - #define CFG_DDR_CLK_CTRL 0x03800000 - #define CFG_DDR_OCD_CTRL 0x00000000 - #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ #define CFG_DDR_CONTROL2 0x04400000 @@ -169,7 +170,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * * Note that, on switching the boot location, fef00000 becomes fff00000. */ -#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ #define CFG_FLASH_BASE2 0xff800000 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} @@ -188,7 +189,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ @@ -203,7 +204,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ @@ -211,7 +212,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -220,7 +221,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CFG_RAMBOOT #endif #if defined(CFG_RAMBOOT) @@ -237,32 +238,32 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #else #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ #endif -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -285,7 +286,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3100 /* @@ -307,13 +308,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ /* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 /* For RTL8139 */ #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 +#define _IO_BASE 0x00000000 #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE @@ -324,12 +325,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #undef CFG_SCSI_SCAN_BUS_REVERSE #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_RTL8139 @@ -339,19 +340,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /************************************************************ * USB support ************************************************************/ -#define CONFIG_PCI_OHCI 1 +#define CONFIG_PCI_OHCI 1 #define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_KEYBOARD 1 #define CFG_DEVICE_DEREGISTER -#define CFG_USB_EVENT_POLL 1 -#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#define CFG_USB_EVENT_POLL 1 +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #define CFG_OHCI_SWAP_REG_ACCESS 1 #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif /*PCIE video card used*/ @@ -383,7 +384,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SATA_ULI5288 #define CFG_SCSI_MAX_SCSI_ID 4 #define CFG_SCSI_MAX_LUN 1 -#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE #endif @@ -394,19 +395,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "eTSEC4" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 @@ -426,76 +427,76 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TSEC_ENET */ /* - * BAT0 2G Cacheable, non-guarded - * 0x0000_0000 2G DDR + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR */ -#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CFG_IBAT0U CFG_DBAT0U +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U /* - * BAT1 1G Cache-inhibited, guarded - * 0x8000_0000 512M PCI-Express 1 Memory - * 0xa000_0000 512M PCI-Express 2 Memory + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ +#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT1U CFG_DBAT1U +#define CFG_IBAT1U CFG_DBAT1U /* - * BAT2 512M Cache-inhibited, guarded - * 0xc000_0000 512M RapidIO Memory + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ +#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) #define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT2U CFG_DBAT2U +#define CFG_IBAT2U CFG_DBAT2U /* - * BAT3 4M Cache-inhibited, guarded - * 0xf800_0000 4M CCSR + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR */ -#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT3U CFG_DBAT3U +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U /* - * BAT4 32M Cache-inhibited, guarded - * 0xe200_0000 16M PCI-Express 1 I/O - * 0xe300_0000 16M PCI-Express 2 I/0 + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ +#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U CFG_DBAT4U +#define CFG_IBAT4U CFG_DBAT4U /* - * BAT5 128K Cacheable, non-guarded - * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) */ -#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_IBAT5L CFG_DBAT5L -#define CFG_IBAT5U CFG_DBAT5U +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U /* - * BAT6 32M Cache-inhibited, guarded - * 0xfe00_0000 32M FLASH + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT6U CFG_DBAT6U +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U #define CFG_DBAT7L 0x00000000 #define CFG_DBAT7U 0x00000000 @@ -556,7 +557,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ @@ -597,7 +598,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD @@ -623,45 +624,45 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=mpc8641_hpcn.dtb\0" \ - "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ - "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ - "maxcpus=2" - - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8641_hpcn.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 831cc5e..e0e8554 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -22,7 +22,7 @@ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ /* CPU type - pick one of these */ -#define CONFIG_MPC866T 1 +#define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T #undef CONFIG_MPC859DSL diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h index f8cf01e..4319e6c 100644 --- a/include/configs/MUSENKI.h +++ b/include/configs/MUSENKI.h @@ -86,7 +86,7 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP #define CONFIG_NET_MULTI /* Multi ethernet cards support */ diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index d799f54..d08d795 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -28,16 +28,16 @@ #define MV_VERSION "v0.2.0" /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */ -#define ERR_NONE 0 -#define ERR_ENV 1 -#define ERR_BOOTM_BADMAGIC 2 -#define ERR_BOOTM_BADCRC 3 -#define ERR_BOOTM_GUNZIP 4 +#define ERR_NONE 0 +#define ERR_ENV 1 +#define ERR_BOOTM_BADMAGIC 2 +#define ERR_BOOTM_BADCRC 3 +#define ERR_BOOTM_GUNZIP 4 #define ERR_BOOTP_TIMEOUT 5 -#define ERR_DHCP 6 -#define ERR_TFTP 7 -#define ERR_NOLAN 8 -#define ERR_LANDRV 9 +#define ERR_DHCP 6 +#define ERR_TFTP 7 +#define ERR_NOLAN 8 +#define ERR_LANDRV 9 #define CONFIG_BOARD_TYPES 1 #define MVBLUE_BOARD_BOX 1 @@ -45,10 +45,10 @@ #if 0 #define ERR_LED(code) do { if (code) \ - *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ - else \ - *(volatile char *)(0xff000003) = ( 1 ); \ - } while(0) + *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ + else \ + *(volatile char *)(0xff000003) = ( 1 ); \ +} while(0) #else #define ERR_LED(code) #endif @@ -116,19 +116,19 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* Max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 /* Default load address */ -#define CONFIG_BOOTCOMMAND "run nfsboot" +#define CONFIG_BOOTCOMMAND "run nfsboot" #define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2" -#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" +#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" #define CONFIG_EXTRA_ENV_SETTINGS \ "console_nr=0\0" \ @@ -156,11 +156,11 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_NET_MULTI -#define CONFIG_NET_RETRY_COUNT 5 +#define CONFIG_NET_RETRY_COUNT 5 #define CONFIG_TULIP #define CONFIG_TULIP_FIX_DAVICOM 1 -#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 +#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 #define CONFIG_HW_WATCHDOG @@ -224,7 +224,7 @@ */ #define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 10000 +#define CFG_HZ 10000 /* Bit-field values for MCCR1. */ #define CFG_ROMNAL 7 diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index 75efd1e..87458e3 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -43,16 +43,19 @@ #undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#define CONFIG_BAUDRATE 115200 /* console baudrate */ #define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ -#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo" +#define CONFIG_PREBOOT "echo;" \ + "echo To mount root over NFS use \"run bootnet\";" \ + "echo To mount root from FLASH use \"run bootflash\";" \ + "echo" #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -61,7 +64,7 @@ #undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ /* @@ -100,9 +103,9 @@ #undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if defined(CONFIG_CMD_KGDB) @@ -193,7 +196,7 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif @@ -267,8 +270,8 @@ #define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ #define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 5346545..0b09482 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -76,12 +76,12 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" -#define CONFIG_WATCHDOG /* watchdog enabled */ +#define CONFIG_WATCHDOG /* watchdog enabled */ #undef CONFIG_STATUS_LED /* Status LED disabled */ @@ -175,7 +175,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index e3c6fd3..27e7ab9 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -66,7 +66,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ + "tftpboot; " \ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" @@ -97,7 +97,7 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 @@ -105,7 +105,7 @@ #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 @@ -292,27 +292,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -322,15 +322,15 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 66666666 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -514,7 +514,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 20404a3..56c76d3 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -64,7 +64,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ + "tftpboot; " \ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" @@ -93,7 +93,7 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY /* do not discover phys */ #define CONFIG_MII 1 @@ -102,15 +102,15 @@ #if defined(CONFIG_NETTA_ISDN) #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ #define CONFIG_FEC1_PHY_NORXERR 1 #undef CONFIG_ETHER_ON_FEC2 #else #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ +#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ #define CONFIG_FEC2_PHY_NORXERR 1 #endif @@ -296,27 +296,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -326,19 +326,19 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 80000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -633,7 +633,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index cf66e04..b8c4848 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -66,9 +66,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_AUTOSCRIPT @@ -98,7 +98,7 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 @@ -106,7 +106,7 @@ #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 @@ -293,27 +293,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -323,15 +323,15 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 66666666 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -515,7 +515,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index af5339e..1293fb0 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -63,9 +63,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ @@ -411,7 +411,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 3929a84..11e5c63 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -295,8 +295,8 @@ #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) #define CFG_PCMCIA_IO_ADDR (0xEC000000) #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ -#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ +#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ +#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ /*----------------------------------------------------------------------- diff --git a/include/configs/NX823.h b/include/configs/NX823.h index da1c173..2a4bd47 100644 --- a/include/configs/NX823.h +++ b/include/configs/NX823.h @@ -127,7 +127,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index e85e1b9..5a2d157 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -42,7 +42,7 @@ #define CONFIG_P3G4 1 /* this is a P3G4 board */ #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ #undef CONFIG_ECC /* enable ECC support */ /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ @@ -417,8 +417,8 @@ #define CFG_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #define L2_ENABLE (L2_INIT | L2CR_L2E) diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 0de7591..4b37eca 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -32,7 +32,7 @@ */ #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ +#define CONFIG_PATI 1 /* ...On a PATI board */ /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 #undef CONFIG_5xx_CONS_SCI2 @@ -74,11 +74,11 @@ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ #define CONFIG_BOOTARGS "" /* */ -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ @@ -123,30 +123,30 @@ /* * Internal Memory Mapped (This is not the IMMR content) */ -#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ +#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ +#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ /* * Start addresses for the final memory configuration * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ #define CFG_FLASH_BASE 0xffC00000 /* External flash */ #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ #define CFG_MONITOR_BASE 0xFFF00000 -/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ +/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -167,9 +167,9 @@ */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_EEPROM @@ -180,8 +180,8 @@ #undef CFG_ENV_IS_IN_FLASH #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ #endif @@ -233,7 +233,7 @@ *----------------------------------------------------------------------- * Data show cycle */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -241,7 +241,7 @@ * Set all bits to 40 Mhz * */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) @@ -251,12 +251,12 @@ *----------------------------------------------------------------------- * */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 24b25d9..abb9bfc 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -54,10 +54,10 @@ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ @@ -87,7 +87,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) /*------------------------------------------------------------------------ * CONSOLE @@ -155,8 +155,8 @@ #define CFG_LONGHELP /* Provide extended help*/ #define CFG_PROMPT "==> " /* Command prompt */ #define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ #define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index b83520d..5890012 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -123,7 +123,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ @@ -252,7 +252,7 @@ #define CFG_TEMP_STACK_OCM 1 #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) diff --git a/include/configs/PM520.h b/include/configs/PM520.h index ad480a6..259178f 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ @@ -159,7 +161,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* * I2C configuration diff --git a/include/configs/PM826.h b/include/configs/PM826.h index cf7314d..36e9aa5 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -47,9 +47,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 38a26dc..9355aaf 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -43,7 +43,7 @@ #define CONFIG_PM856 1 /* PM856 board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -92,7 +92,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -141,7 +141,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -167,16 +167,16 @@ #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ @@ -236,7 +236,7 @@ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -244,7 +244,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -256,7 +256,7 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 72acf5a..da7d8b8 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -73,7 +73,7 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 +#define CONFIG_IPADDR 10.0.0.200 #define CONFIG_ROOTPATH /opt/eldk/ppc_82xx #define CONFIG_NETMASK 255.255.255.0 #undef CONFIG_BOOTARGS @@ -81,7 +81,7 @@ /* Boot Linux with NFS root filesystem */ #define CONFIG_BOOTCOMMAND \ "setenv verify y;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 100000; bootm" @@ -90,7 +90,7 @@ /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ #define CONFIG_BOOTCOMMAND \ "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/ram rw " \ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 200000; bootm" @@ -128,7 +128,7 @@ /* * Networking stuff */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ #define CONFIG_PCNET_79C973 @@ -153,9 +153,9 @@ /*#define CFG_GBL_DATA_SIZE 256*/ #define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_NO_FLASH 1 /* There is no FLASH memory */ diff --git a/include/configs/QS823.h b/include/configs/QS823.h index 3dd84e8..cef9f42 100644 --- a/include/configs/QS823.h +++ b/include/configs/QS823.h @@ -492,12 +492,12 @@ /* For boards with 16M of SDRAM */ #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* For boards with 32M of SDRAM */ #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) diff --git a/include/configs/QS850.h b/include/configs/QS850.h index 7dd6eca..ba5827a 100644 --- a/include/configs/QS850.h +++ b/include/configs/QS850.h @@ -492,12 +492,12 @@ /* For boards with 16M of SDRAM */ #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* For boards with 32M of SDRAM */ #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index f4aecfc..a653cca 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -62,9 +62,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #undef CONFIG_SCC1_ENET diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index e3c7561..9222d21 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -65,9 +65,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index 793b1db..706e2aa 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -78,9 +78,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -467,7 +467,7 @@ #define BCSR3 0xFA400003 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 3c5e6b8..671094b 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -51,9 +51,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -156,7 +156,7 @@ #define CFG_DIRECT_FLASH_TFTP #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CONFIG_ENV_OVERWRITE @@ -361,7 +361,7 @@ #define BCSR3 0xFA400003 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 32e2285..6a71801 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -119,7 +119,7 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ # define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */ # define CFG_I2C_SLAVE 0xFE diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 428c0c2..01ebc8f 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -250,13 +250,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 946b3c2..ff64378 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -48,7 +48,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ +#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h index bc5389f..febfc39 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -67,9 +67,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ @@ -165,7 +165,7 @@ * - Enable Full Duplex in FSMR */ # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h index 4d9d41b..31853c8 100644 --- a/include/configs/SL8245.h +++ b/include/configs/SL8245.h @@ -90,10 +90,10 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } #define CFG_RESET_ADDRESS 0xFFF00100 diff --git a/include/configs/SM850.h b/include/configs/SM850.h index 41a54f0..465db47 100644 --- a/include/configs/SM850.h +++ b/include/configs/SM850.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index 8f2a5ec..3aee45c 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -204,7 +204,7 @@ #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 @@ -250,7 +250,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 6cb3022..d21783b 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 1affcfd..4c44735 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ @@ -176,7 +178,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * I2C configuration diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index 8237ba1..151c407 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -201,10 +201,10 @@ * defines we need to get FEC running */ #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ -#define FEC_ENET 1 /* eth.c needs it that way... */ +#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ +#define FEC_ENET 1 /* eth.c needs it that way... */ #define CFG_DISCOVER_PHY 1 -#define CONFIG_MII 1 +#define CONFIG_MII 1 #define CONFIG_MII_INIT 1 #define CONFIG_PHY_ADDR 31 @@ -287,7 +287,7 @@ *----------------------------------------------------------------------- * set up SYPCR: * 16 SWTC 0xffff Software watchdog timer count - * 8 BMT 0xff Bus monitor timing + * 8 BMT 0xff Bus monitor timing * 1 BME 1 Bus monitor enable * 3 0 000 * 1 SWF 1 Software watchdog freeze @@ -297,7 +297,7 @@ */ #if defined (CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) #endif diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index bff2edf..bfb478a 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -47,6 +47,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 02a16ac..89fc465 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -176,7 +176,7 @@ extern int tqm834x_num_flash_banks; #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -231,7 +231,7 @@ extern int tqm834x_num_flash_banks; /* * TSEC */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MII #define CFG_TSEC1_OFFSET 0x24000 @@ -423,6 +423,8 @@ extern int tqm834x_num_flash_banks; #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 2507d77..598fe7b 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -48,6 +48,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ @@ -178,7 +180,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index df6894f..ad8db61 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -44,7 +44,7 @@ #define USE_920T_MMU 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 @@ -84,8 +84,8 @@ * address 0x50 with 16bit addressing ***********************************************************/ #define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_I2C_EEPROM_ADDR_LEN 2 @@ -111,7 +111,7 @@ */ #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ #define CS8900_BASE 0x20000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ @@ -145,7 +145,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 10.0.0.110 @@ -262,7 +262,7 @@ #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index 1405784..db05d82 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -369,7 +369,7 @@ /* * MEMORY MAP * ---------- - * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) + * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) * CS1 - SDRAM 32MB/64Bit base=0x00000000 * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000 * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000 diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 7017fff..bb6b6b9 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -154,10 +154,10 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Set up values for external bus controller diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index bfb3156..3050caf 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -161,10 +161,10 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Set up values for external bus controller diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 00c4ff0..1b4195a 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_YUKON8220 1 /* ... on Yukon board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index 7c1a5b9..b04be76 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -200,13 +200,13 @@ HRCW_MODCK_H0111 \ ) /* 0x16848207 */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 81e7c1e..4226529 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -45,14 +45,25 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ +#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ + +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif /* CONFIG_PCI is defined at config time */ #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R #define CFG_IMMR 0x80000000 +#define CFG_DIU_ADDR (CFG_IMMR+0x2100) #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 @@ -127,28 +138,28 @@ #define CFG_MICRON_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ -#define CFG_MDDRCGRP_PM_CFG1 0x000777AA -#define CFG_MDDRCGRP_PM_CFG2 0x00000055 -#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000 -#define CFG_MDDRCGRP_LUT0_MU 0x11111117 -#define CFG_MDDRCGRP_LUT0_ML 0x7777777A -#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE -#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE -#define CFG_MDDRCGRP_LUT2_MU 0x44444444 +#define CFG_MDDRCGRP_PM_CFG1 0x00077777 +#define CFG_MDDRCGRP_PM_CFG2 0x00000000 +#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CFG_MDDRCGRP_LUT1_MU 0x66666666 +#define CFG_MDDRCGRP_LUT1_ML 0x55555555 +#define CFG_MDDRCGRP_LUT2_MU 0x44444444 #define CFG_MDDRCGRP_LUT2_ML 0x44444444 -#define CFG_MDDRCGRP_LUT3_MU 0x55555555 +#define CFG_MDDRCGRP_LUT3_MU 0x55555555 #define CFG_MDDRCGRP_LUT3_ML 0x55555558 -#define CFG_MDDRCGRP_LUT4_MU 0x11111111 -#define CFG_MDDRCGRP_LUT4_ML 0x1111117C -#define CFG_MDDRCGRP_LUT0_AU 0x33333377 -#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE -#define CFG_MDDRCGRP_LUT1_AU 0x11111111 -#define CFG_MDDRCGRP_LUT1_AL 0x11111111 -#define CFG_MDDRCGRP_LUT2_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_MU 0x11111111 +#define CFG_MDDRCGRP_LUT4_ML 0x11111122 +#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CFG_MDDRCGRP_LUT1_AU 0x66666666 +#define CFG_MDDRCGRP_LUT1_AL 0x66666666 +#define CFG_MDDRCGRP_LUT2_AU 0x11111111 #define CFG_MDDRCGRP_LUT2_AL 0x11111111 -#define CFG_MDDRCGRP_LUT3_AU 0x11111111 +#define CFG_MDDRCGRP_LUT3_AU 0x11111111 #define CFG_MDDRCGRP_LUT3_AL 0x11111111 -#define CFG_MDDRCGRP_LUT4_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_AU 0x11111111 #define CFG_MDDRCGRP_LUT4_AL 0x11111111 /* @@ -161,7 +172,7 @@ #define CFG_FLASH_USE_BUFFER_WRITE #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM @@ -189,7 +200,11 @@ #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ +#ifdef CONFIG_FSL_DIU_FB +#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ +#else +#define CFG_MALLOC_LEN (512 * 1024) +#endif /* * Serial Port @@ -357,6 +372,8 @@ #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Internal Definitions * diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h index 703d312..427b548 100644 --- a/include/configs/adsvix.h +++ b/include/configs/adsvix.h @@ -359,7 +359,7 @@ /* Flash environment locations */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ #endif /* __CONFIG_H */ diff --git a/include/configs/aev.h b/include/configs/aev.h index e3f810c..c5e4759 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -41,6 +41,8 @@ #define CONFIG_AEVFIFO 1 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 294cd26..8973296 100755..100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -174,7 +174,7 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ #define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index 73a8885..98a83db 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -41,9 +41,9 @@ * (easy to change) */ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ +#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -88,7 +88,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" +#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" #define CONFIG_BOOTCOMMAND "bootm 40000 180000" diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index c891fa8..342ce2a 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -28,6 +28,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91CAP9" #define AT91_MAIN_CLOCK 200000000 /* from 12 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ #define CFG_HZ 1000000 /* 1us resolution */ @@ -55,11 +56,19 @@ #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock1 rw rootfstype=jffs2" +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 -/* #define CONFIG_ENV_OVERWRITE 1 */ +#define CONFIG_BOOTDELAY 3 /* * BOOTP options @@ -94,9 +103,9 @@ #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) #define CFG_MAX_DATAFLASH_BANKS 1 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define AT91_SPI_CLK 20000000 -#define DATAFLASH_TCSS (0xFA << 16) -#define DATAFLASH_TCHS (0x8 << 24) +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) /* NOR flash */ #define CFG_FLASH_CFI 1 @@ -110,6 +119,7 @@ #define NAND_MAX_CHIPS 1 #define CFG_MAX_NAND_DEVICE 1 #define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 /* Ethernet */ #define CONFIG_MACB 1 @@ -143,7 +153,12 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=physmap-flash.0:-(nor);" \ + "at91_nand:-(root) " \ + "rw rootfstype=jffs2" #else @@ -154,6 +169,12 @@ #define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4000 #define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock4 " \ + "mtdparts=physmap-flash.0:16k(bootstrap)ro,"\ + "16k(env),224k(uboot)ro,-(linux);" \ + "at91_nand:-(root) " \ + "rw rootfstype=jffs2" #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 41c418f..675224e 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -56,10 +56,6 @@ #define CONFIG_USART3 1 /* USART 3 is DBGU */ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock0 rw rootfstype=jffs2" - -/* #define CONFIG_ENV_OVERWRITE 1 */ /* * BOOTP options @@ -96,7 +92,7 @@ #define CFG_MAX_DATAFLASH_BANKS 2 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ -#define AT91_SPI_CLK 33000000 +#define AT91_SPI_CLK 15000000 #define DATAFLASH_TCSS (0x1a << 16) #define DATAFLASH_TCHS (0x1 << 24) @@ -104,6 +100,7 @@ #define NAND_MAX_CHIPS 1 #define CFG_MAX_NAND_DEVICE 1 #define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 /* NOR flash - no real flash on this board */ #define CFG_NO_FLASH 1 @@ -142,7 +139,11 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" #elif CFG_USE_DATAFLASH_CS1 @@ -152,7 +153,11 @@ #define CFG_ENV_OFFSET 0x4200 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" #else /* CFG_USE_NANDFLASH */ @@ -162,6 +167,12 @@ #define CFG_ENV_OFFSET_REDUND 0x80000 #define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h new file mode 100644 index 0000000..e53a23f --- /dev/null +++ b/include/configs/at91sam9261ek.h @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Configuation settings for the AT91SAM9261EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9261" +#define AT91_MAIN_CLOCK 198656000 /* from 18.432 MHz crystal */ +#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* NOR flash - no real flash on this board */ +#define CFG_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9261" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH_CS0 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h new file mode 100644 index 0000000..a8194b5 --- /dev/null +++ b/include/configs/at91sam9263ek.h @@ -0,0 +1,206 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Configuation settings for the AT91SAM9263EK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9263" +#define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */ +#define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash, if populated */ +#if 1 +#define CFG_NO_FLASH 1 +#else +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_MAX_FLASH_BANKS 1 +#endif + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9263" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h new file mode 100644 index 0000000..2ad8d05 --- /dev/null +++ b/include/configs/at91sam9rlek.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Configuation settings for the AT91SAM9RLEK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9RL" +#define AT91_MAIN_CLOCK 200000000 /* from 12.000 MHz crystal */ +#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */ +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ +#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_RGB565 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_BOOTDELAY 3 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_USB + +#define CONFIG_CMD_NAND 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash - not present */ +#define CFG_NO_FLASH 1 + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* Ethernet - not present */ + +/* USB - not supported */ + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_DATAFLASH 1 +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CFG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CFG_ENV_OFFSET 0x4200 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#else /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x60000 +#define CFG_ENV_OFFSET_REDUND 0x80000 +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/atc.h b/include/configs/atc.h index 4ef50c2..285b4e4 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -111,7 +111,7 @@ #define CONFIG_BOOTCOMMAND \ "bootp;" \ "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ + "nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ "bootm" @@ -182,9 +182,9 @@ #define CONFIG_RTC_DS12887 -#define RTC_BASE_ADDR 0xF5000000 -#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 -#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 +#define RTC_BASE_ADDR 0xF5000000 +#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 +#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 #define CONFIG_MISC_INIT_R diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 5aad043..3fc9975 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7000 1 @@ -112,8 +114,11 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC + +#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 @@ -137,11 +142,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 -#define CFG_SDRAM_16BIT 1 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -150,27 +153,20 @@ #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) #define CFG_MALLOC_LEN (256*1024) -#define CFG_MALLOC_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - CFG_SDRAM_BASE + gd->sdram_size; \ - }) -#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) - #define CFG_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 95aeab6..ba18eb6 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7000 1 @@ -139,9 +141,9 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC -#define CONFIG_CMD_REGINFO #undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_XIMG @@ -170,10 +172,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -185,17 +186,17 @@ #define CFG_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 -#define CFG_MAXARGS 8 +#define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 194788b..a528ddf 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7001 1 @@ -153,10 +155,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -167,17 +168,17 @@ #define CFG_MALLOC_LEN (256*1024) /* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index b81fc21..fc9585e 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -24,6 +24,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/memory-map.h> + #define CONFIG_AVR32 1 #define CONFIG_AT32AP 1 #define CONFIG_AT32AP7002 1 @@ -153,11 +155,9 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_INTRAM_BASE 0x24000000 -#define CFG_INTRAM_SIZE 0x8000 - -#define CFG_SDRAM_BASE 0x10000000 -#define CFG_SDRAM_16BIT 1 +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 65536 @@ -168,17 +168,17 @@ #define CFG_MALLOC_LEN (256*1024) /* Allow 2MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000) #define CFG_BOOTPARAMS_LEN (16 * 1024) /* Other configuration settings that shouldn't have to change all that often */ -#define CFG_PROMPT "Uboot> " +#define CFG_PROMPT "U-Boot> " #define CFG_CBSIZE 256 #define CFG_MAXARGS 16 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_START EBI_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h new file mode 100644 index 0000000..9fd49a5 --- /dev/null +++ b/include/configs/atstk1006.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Configuration settings for the ATSTK1002 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/memory-map.h> + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_ATSTK1006 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=mtd3 fbmem=2400k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ diff --git a/include/configs/barco.h b/include/configs/barco.h index 0bb446f..4f57067 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -96,8 +96,8 @@ #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTCOMMAND "boot_default" +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND "boot_default" /* * Miscellaneous configurable options @@ -135,9 +135,9 @@ #define CONFIG_LOGBUFFER #ifdef CONFIG_LOGBUFFER -#define CFG_STDOUT_ADDR 0x1FFC000 +#define CFG_STDOUT_ADDR 0x1FFC000 #else -#define CFG_STDOUT_ADDR 0x2B9000 +#define CFG_STDOUT_ADDR 0x2B9000 #endif #define CFG_RESET_ADDRESS 0xFFF00100 @@ -158,9 +158,9 @@ #define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 66a0af6..d70aa10 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -25,7 +25,7 @@ #define CONFIG_SMC91111_BASE 0x20300300 /* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 +#define SHARED_RESOURCES 1 /* Is I2C bit-banged? */ #define CONFIG_SOFT_I2C 1 @@ -112,7 +112,7 @@ #endif #define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ #define ENV_IS_EMBEDDED #define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ @@ -123,7 +123,7 @@ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 /* * following timeouts shall be used once the @@ -148,7 +148,7 @@ #define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1) #define CONFIG_LOADADDR 0x01000000 -#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_LOAD_ADDR CONFIG_LOADADDR #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 39c7359..a881d53 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -103,11 +103,11 @@ #define CFG_LONGHELP 1 #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ -#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTCOMMAND "run ramboot" #if defined(CONFIG_POST_TEST) /* POST support */ -#define CONFIG_POST ( CFG_POST_MEMORY | \ +#define CONFIG_POST ( CFG_POST_MEMORY | \ CFG_POST_UART | \ CFG_POST_FLASH | \ CFG_POST_ETHER | \ @@ -208,7 +208,7 @@ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024) +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024) #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -281,10 +281,10 @@ #define NAND_MAX_CHIPS 1 #define BFIN_NAND_READY PF3 -#define NAND_WAIT_READY(nand) \ - do { \ - int timeout = 0; \ - while(!(*pPORTFIO & PF3)) \ +#define NAND_WAIT_READY(nand) \ + do { \ + int timeout = 0; \ + while(!(*pPORTFIO & PF3)) \ if (timeout++ > 100000) \ break; \ } while (0) diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 641548d..e99e979 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -148,28 +148,27 @@ #if (CONFIG_DRIVER_SMC91111) #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ - "$(rootpath) console=ttyBF0,57600\0" \ + "$(rootpath) console=ttyBF0,57600\0" \ "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux; " \ + "ramboot=tftpboot $(loadaddr) linux; " \ "run ramargs; run addip; bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux; " \ + "nfsboot=tftpboot $(loadaddr) linux; " \ "run nfsargs; run addip; bootelf\0" \ - "update=tftpboot $(loadaddr) u-boot.bin; " \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ "protect off 0x20000000 0x2003FFFF; " \ "erase 0x20000000 0x2003FFFF; " \ - "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ "" #else #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "flashboot=bootm 0x20100000\0" \ "" #endif - /* * BOOTP options */ @@ -178,7 +177,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -193,7 +191,6 @@ #define CONFIG_CMD_DHCP #endif - /* * Console settings */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index cbd74a0..75dd4e7 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -302,7 +302,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index a5621b8..6f0d4b0 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 440972c..f097e2c 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -31,7 +31,7 @@ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ -#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ +#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ @@ -115,7 +117,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * Flash configuration, expect one 16 Megabyte Bank at most diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index e06735d..c801f03 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -39,7 +39,7 @@ #define BOARD_LATE_INIT 1 #define CONFIG_BAUDRATE 38400 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* * Size of malloc() pool @@ -104,7 +104,7 @@ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #endif #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -137,21 +137,21 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ #define CFG_DRAM_BASE 0xa0000000 #define CFG_DRAM_SIZE 0x04000000 @@ -210,7 +210,7 @@ * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index d554348..ef50c7c 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,6 +31,8 @@ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Supported commands */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index a869364..ac2b7a1 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -24,7 +24,7 @@ * File: cmi_mpc5xx.h * * Discription: Config header file for cmi - * board using an MPC5xx CPU + * board using an MPC5xx CPU * */ @@ -36,7 +36,7 @@ */ #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_CMI 1 /* Using the customized cmi board */ +#define CONFIG_CMI 1 /* Using the customized cmi board */ /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 @@ -79,11 +79,11 @@ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ #define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ #define CONFIG_STATUS_LED 1 /* Enable status led */ @@ -121,30 +121,30 @@ /* * Internal Memory Mapped (This is not the IMMR content) */ -#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ +#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ +#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ /* * Start addresses for the final memory configuration * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ #define CFG_FLASH_BASE 0x02000000 /* External flash */ #define PLD_BASE 0x03000000 /* PLD */ #define ANYBUS_BASE 0x03010000 /* Anybus Module */ #define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ @@ -163,16 +163,16 @@ */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ #define CFG_FLASH_PROTECTION 1 /* Physically section protection on */ #define CFG_ENV_IS_IN_FLASH 1 #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ #endif @@ -219,7 +219,7 @@ *----------------------------------------------------------------------- * Data show cycle */ -#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ +#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -227,7 +227,7 @@ * Set all bits to 40 Mhz * */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) @@ -236,12 +236,12 @@ *----------------------------------------------------------------------- * */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register @@ -256,7 +256,7 @@ #define CFG_OR2_PRELIM (OR_ADDR_MK_FF) #define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) #define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ - OR_ACS_10 | OR_ETHR | OR_CSNT) + OR_ACS_10 | OR_ETHR | OR_CSNT) #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index c7e3899..649b053 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -101,7 +101,7 @@ * bootloader residing in flash ('chainloading'); if you want to use * chainloading or want to compile a u-boot binary that can be loaded into * RAM via BDM set - * "#if 0" to "#if 1" + * "#if 0" to "#if 1" * You will need a first stage bootloader then, e. g. colilo or a working BDM * cable (Background Debug Mode) * @@ -165,7 +165,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 1b30e51..fffd1fe 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 0be0f21..a807d00 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -37,7 +37,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_CSB226 1 /* on a CSB226 board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index a24478d..15bf177 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ @@ -182,7 +182,7 @@ */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 064650c..b06c0a2 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ @@ -181,7 +181,7 @@ */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 8ecd059..632c4c2 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -145,16 +145,16 @@ #define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ #define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3) -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ #define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ #define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ #endif /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #undef CONFIG_BOOTDELAY #define CONFIG_BOOTFILE "uImage" /* Boot file name */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 96c9a30..10166a1 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -102,7 +102,7 @@ /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #undef CONFIG_BOOTDELAY #define CONFIG_BOOTFILE "uImage" /* Boot file name */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index de8c4fa..ba68605 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -140,16 +140,16 @@ #define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ #define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2) -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ #define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ #define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ #endif /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #undef CONFIG_BOOTDELAY #define CONFIG_BOOTFILE "uImage" /* Boot file name */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index d32e046..e7873e9 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -83,7 +83,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" #define CONFIG_ETHADDR 02:80:ad:20:31:b8 #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 172.22.2.23 diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h index f5cf477..5433082 100644 --- a/include/configs/ep7312.h +++ b/include/configs/ep7312.h @@ -34,7 +34,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_EP7312 1 /* on an EP7312 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -81,8 +81,8 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" -#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 /*#define CONFIG_NETMASK 255.255.0.0 */ /*#define CONFIG_IPADDR 172.22.2.128 */ /*#define CONFIG_SERVERIP 172.22.2.126 */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index cebe849..8a220b6 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -234,13 +234,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 490db5f..0ce6b80 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -28,17 +28,17 @@ * board/config.h - configuration options, board specific * * "EP8260 H, V.1.1" - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 16M Flash (4 x AM29DL323DB90WDI) - * - 128k NVRAM with RTC + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 16M Flash (4 x AM29DL323DB90WDI) + * - 128k NVRAM with RTC * * "EP8260 H2, V.1.3" (CFG_EP8260_H2) - * - 300MHz/133MHz/66MHz - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 32M Flash - * - 128k NVRAM with RTC + * - 300MHz/133MHz/66MHz + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 32M Flash + * - 128k NVRAM with RTC */ #ifndef __CONFIG_H @@ -408,7 +408,7 @@ CFG_SBC_HRCW_IMMR |\ HRCW_APPC10 |\ HRCW_CS10PC01 |\ - CFG_SBC_MODCK_H |\ + CFG_SBC_MODCK_H |\ CFG_SBC_HRCW_BOOT_FLAGS) #else #define CFG_HRCW_MASTER 0x10400245 diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 8e5d6e5..ac5847c 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -229,7 +229,7 @@ #endif /* CFG_ENV_IS_IN_EEPROM */ /* RTC Configuration */ -#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ +#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ #define CFG_I2C_RTC_ADDR 0x68 #define CONFIG_M41T11_BASE_YEAR 1900 @@ -353,13 +353,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index 66500c2..1571477 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -98,7 +98,7 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTCOMMAND "tftp 100000 uImage" -/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ +/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index 1276f4d..ffe7671 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -58,7 +58,7 @@ #define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */ +#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 710a082..7b1d582 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -39,10 +39,10 @@ #define CONFIG_LEON3 /* This is an LEON3 CPU */ #define CONFIG_LEON 1 /* This is an LEON CPU */ /* Altera NIOS Development board, Stratix II board */ -#define CONFIG_GR_EP2S60 1 +#define CONFIG_GR_EP2S60 1 /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */ +#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index 1fdef3d..6fe2b7c 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -39,7 +39,7 @@ #define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */ /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ +#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 60ad396..3fb8eb3 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -46,7 +46,7 @@ #define CONFIG_TSIM 1 /* ... running on TSIM */ /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ +#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 2ad5b95..406ce3d 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -45,7 +45,7 @@ #define CONFIG_TSIM 1 /* ... running on TSIM */ /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ +#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 4ecaf90..13b0358 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -127,14 +127,14 @@ #ifdef CFG_ENV_IS_IN_EEPROM /* Put the environment after the SDRAM configuration */ -#define PROM_SIZE 2048 +#define PROM_SIZE 2048 #define CFG_ENV_OFFSET 512 #define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) #endif #ifdef CFG_ENV_IS_IN_FLASH /* Put the environment in Flash */ -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index f5f1197..2080868 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -113,7 +113,7 @@ #ifdef CFG_ENV_IS_IN_EEPROM /* Put the environment after the SDRAM and bootstrap configuration */ -#define PROM_SIZE 2048 +#define PROM_SIZE 2048 #define CFG_BOOSTRAP_OPTION_OFFSET 512 #define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10) #define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) @@ -134,7 +134,7 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ +#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ #define CFG_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */ #undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ #define CONFIG_DDR_ECC 1 /* enable ECC */ @@ -176,13 +176,13 @@ /* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME hcu5 #define CONFIG_IPADDR 172.25.1.99 -#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ #define CONFIG_OVERWRITE_ETHADDR_ONCE #define CONFIG_SERVERIP 172.25.1.3 #define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=0x01000000\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -192,11 +192,11 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "bootfile=hcu5/uImage\0" \ - "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ - "load=tftp 100000 hcu5/u-boot.bin\0" \ + "bootfile=hcu5/uImage\0" \ + "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ + "load=tftp 100000 hcu5/u-boot.bin\0" \ "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \ "cp.b 100000 FFFB0000 50000\0" \ "upd=run load update\0" \ @@ -204,9 +204,9 @@ "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \ "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \ - "usbargs=setenv bootargs root=/dev/sda1 ro\0" \ + "usbargs=setenv bootargs root=/dev/sda1 ro\0" \ "linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \ - "run usbargs addip addtty; bootm\0" \ + "run usbargs addip addtty; bootm\0" \ "net_nfs_fdt=tftp 200000 ${bootfile};" \ "tftp ${fdt_addr} ${fdt_file};" \ "run nfsargs addip addtty;" \ diff --git a/include/configs/hermes.h b/include/configs/hermes.h index e3a2ed2..48b23bd 100644 --- a/include/configs/hermes.h +++ b/include/configs/hermes.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -105,7 +105,7 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ +#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -227,7 +227,7 @@ /* +0x0282 => 0x03800000 */ #define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000) diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index e5a8897..ad7cf76 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 2ed51f7..7c3ebad 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -164,7 +164,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/impa7.h b/include/configs/impa7.h index 0e52ffe..e9704fc 100644 --- a/include/configs/impa7.h +++ b/include/configs/impa7.h @@ -34,7 +34,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_IMPA7 1 /* on an impA7 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ +#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -80,7 +80,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5a */ /*#define CONFIG_NETMASK 255.255.0.0 */ /*#define CONFIG_IPADDR 172.22.2.128 */ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 4281d73..ec4ed1e 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -65,7 +65,8 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 -#define CONFIG_MXC_SPI_IFACE 1 +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index c89f041..6ec92c3 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -40,6 +40,8 @@ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 5310e0d..2b65052 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -34,7 +34,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -136,11 +136,11 @@ /* * I2C bus */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xfe +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xfe -#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_IS_IN_EEPROM 1 #define CFG_ENV_OFFSET 0x00 /* environment starts here */ #define CFG_ENV_SIZE 1024 /* 1 KiB */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index e1d1483..347fa02 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -140,7 +140,7 @@ SIB at Block62 End Block62 address 0x24f80000 */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ /*----------------------------------------------------------------------- * FLASH and environment organization @@ -156,9 +156,9 @@ SIB at Block62 End Block62 address 0x24f80000 */ #define CFG_FLASH_BASE 0x24000000 -#define CFG_MAX_FLASH_SECT 64 +#define CFG_MAX_FLASH_SECT 64 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index bc5f9e1..b7c43fe 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -165,7 +165,7 @@ */ #define CFG_SDR_CONFIG 0xd #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * GPIO settings @@ -178,7 +178,7 @@ * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -193,7 +193,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index a3be0b5..05dc841 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -201,13 +201,13 @@ */ #define CFG_SDR_CONFIG 0x18 #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -225,7 +225,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 0ac3e7e..c985927 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -41,6 +41,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ @@ -142,7 +144,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #if 0 /* pass open firmware flat tree */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index c7c42a4..a596768 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -108,7 +108,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 48d73ac..7655666 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -225,7 +225,7 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ /* buffers & descriptors */ #define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ @@ -308,7 +308,7 @@ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ + /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -339,7 +339,7 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ /* CFG_PCI_MEMBASE */ /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT diff --git a/include/configs/lart.h b/include/configs/lart.h index 8f18c9f..4570398 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -76,7 +76,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 172.22.2.131 diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 518186b..d3908b9 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -114,9 +114,9 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ -#define CONFIG_BOOTCOMMAND "run bootcmd1" +#define CONFIG_BOOTCOMMAND "run bootcmd1" #define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug" -#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" +#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" #define CFG_CONSOLE_IS_IN_ENV @@ -214,28 +214,28 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_FLASH_BASE 0xFFC00000 #define CFG_FLASH_SIZE 0x00400000 -#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_RESET_ADDRESS 0xFFF00100 -#define CFG_EUMB_ADDR 0x80000000 +#define CFG_RESET_ADDRESS 0xFFF00100 +#define CFG_EUMB_ADDR 0x80000000 #define CFG_PCI_MEM_ADDR 0xB0000000 #define CFG_MISC_REGION_ADDR 0xFE000000 -#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ +#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ /* Maximum amount of RAM */ #if defined(CONFIG_HLAN) || defined(CONFIG_LAN) -#define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ +#define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) -#define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ +#define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ #else #error Unknown LinkStation type #endif diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 2b2d377..047b4a4 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -34,7 +34,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 1f669aa..cf406c8 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -88,15 +88,20 @@ /* unused GPT0 COMP reg */ #define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */ +#define CFG_OCM_SIZE (16 << 10) /* Additional registers for watchdog timer post test */ #define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2) #define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1) #define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR +#define CFG_OCM_STATUS_ADDR CFG_WATCHDOG_FLAGS_ADDR #define CFG_WATCHDOG_MAGIC 0x12480000 #define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000 #define CFG_DSPIC_TEST_MASK 0x00000001 +#define CFG_OCM_STATUS_OK 0x00009A00 +#define CFG_OCM_STATUS_FAIL 0x0000A300 +#define CFG_OCM_STATUS_MASK 0x0000FF00 /*----------------------------------------------------------------------- * Serial Port @@ -162,6 +167,7 @@ CFG_POST_FPU | \ CFG_POST_I2C | \ CFG_POST_MEMORY | \ + CFG_POST_OCM | \ CFG_POST_RTC | \ CFG_POST_SPR | \ CFG_POST_UART | \ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 67243d4..af066f3 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -101,7 +101,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index a9c86f9..e4c3f72 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration * diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index c5b6e8f..4e9645e 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -45,7 +45,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ +#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ @@ -54,13 +54,13 @@ #define CFG_MONITOR_BASE TEXT_BASE /* ... with on-chip memory here (4KBytes) */ -#define CFG_OCM_DATA_ADDR 0xF4000000 -#define CFG_OCM_DATA_SIZE 0x00001000 +#define CFG_OCM_DATA_ADDR 0xF4000000 +#define CFG_OCM_DATA_SIZE 0x00001000 /* Do not set up locked dcache as init ram. */ #undef CFG_INIT_DCACHE_CS /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -#define CFG_TEMP_STACK_OCM 1 +#define CFG_TEMP_STACK_OCM 1 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE @@ -127,7 +127,7 @@ #ifdef CFG_ENV_IS_IN_EEPROM /* Put the environment after the SDRAM configuration */ -#define PROM_SIZE 2048 +#define PROM_SIZE 2048 #define CFG_ENV_OFFSET 512 #define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) #endif diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 49919fb..8dfb9aa 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ @@ -154,7 +156,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif /* * I2C configuration diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 2924acc..59ff96b 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -188,13 +188,13 @@ #define CFG_HRCW_MASTER 0x0604b211 /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h index 4461bdf..5159897 100644 --- a/include/configs/modnet50.h +++ b/include/configs/modnet50.h @@ -90,7 +90,8 @@ /*#define CONFIG_BOOTDELAY 10*/ /* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */ #define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000" -#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd" +#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K " \ + "root=/dev/ram keepinitrd" #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 1503598..b6843af 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -35,6 +35,7 @@ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * BOOTP options diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index f614e67..a218f75 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -39,7 +39,7 @@ #define CONFIG_MPC7448HPC2 #define CONFIG_74xx -#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CONFIG_ALTIVEC /* undef to disable */ #define CFG_BOARD_NAME "MPC7448 HPC II" diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index 9c94c4e..5e79a27 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -96,7 +96,7 @@ #define CFG_ENV_SECT_SIZE (64 * 1024) #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_ERASE_TOUT 120000 #define CFG_FLASH_WRITE_TOUT 500 /* Board Clock */ diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 8538037..8d92a13 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -39,7 +39,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" +#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.0.22 #define CONFIG_SERVERIP 192.168.0.1 @@ -86,7 +86,7 @@ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ #define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image - in Flash (NOT run time address in SDRAM) ?!? */ + in Flash (NOT run time address in SDRAM) ?!? */ #define CFG_MONITOR_LEN (128 * 1024) /* */ #define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ @@ -101,7 +101,7 @@ #define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ #define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each - Flash chip */ + Flash chip */ /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ #define CFG_MAX_FLASH_BANKS 2 @@ -123,7 +123,7 @@ #define CFG_ENV_SECT_SIZE (8 * 1024) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE)) -#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */ +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE)) diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index a25364d..3000c77 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -48,7 +48,7 @@ #define BOARD_LATE_INIT 1 #define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "console=ttySC0,38400" +#define CONFIG_BOOTARGS "console=ttySC0,38400" #define CONFIG_ENV_OVERWRITE 1 /* SDRAM */ @@ -71,8 +71,8 @@ /* #define CFG_FLASH_BASE (0xA1000000)*/ #define CFG_FLASH_BASE (0xA0000000) #define CFG_MAX_FLASH_BANKS (1) /* Max number of - * Flash memory banks - */ + * Flash memory banks + */ #define CFG_MAX_FLASH_SECT 142 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } @@ -96,7 +96,7 @@ #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_ERASE_TOUT 120000 #define CFG_FLASH_WRITE_TOUT 500 /* Board Clock */ diff --git a/include/configs/munices.h b/include/configs/munices.h index 38b27bb..e0046ec 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -35,6 +35,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Command line configuration. diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 2ea48a6..37ba872 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -62,7 +62,8 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 -#define CONFIG_MXC_SPI_IFACE 1 /* Default SPI interface number */ +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/netstar.h b/include/configs/netstar.h index a48893d..d4deda4 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -180,16 +180,16 @@ "if test -n $swapos; then " \ "setenv swapos; saveenv; " \ "else " \ - "if test $ospart -eq 0; then setenv ospart 1;" \ - "else setenv ospart 0; fi; " \ + "if test $ospart -eq 0; then setenv ospart 1;" \ + "else setenv ospart 0; fi; " \ "fi\0" \ "nfsargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ "nfsroot=$rootpath root=/dev/nfs\0" \ "flashargs=run setpart;setenv bootargs $bootargs " \ "root=mtd:rootfs$ospart ro " \ "rootfstype=jffs2\0" \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ "fboot=run flashargs;nboot kernel$ospart\0" \ "nboot=bootp;run nfsargs;tftp\0" diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h index 1d691f9..f30cb46 100644 --- a/include/configs/ns9750dev.h +++ b/include/configs/ns9750dev.h @@ -62,7 +62,7 @@ /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 1 /* Port B */ +#define CONFIG_CONS_INDEX 1 /* Port B */ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -93,7 +93,7 @@ #define CONFIG_BOOTDELAY 3 -/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ +/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ #define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ #define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 8dde1ef..88bdb03 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 45dc343..0913b14 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -42,6 +42,7 @@ #if defined (CONFIG_P3M750) #define CONFIG_750FX /* 750GL/GX/FX */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CFG_BOARD_NAME "P3M750" #define CFG_BUS_HZ 100000000 #define CFG_BUS_CLK CFG_BUS_HZ @@ -138,9 +139,9 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #if defined (CONFIG_P3M750) -#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device)*/ +#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */ #elif defined (CONFIG_P3M7448) -#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ +#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ #endif #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index e3c8843..7e393f7 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -228,7 +228,7 @@ #if 0 /* Start port with environment in flash; switch to SPI EEPROM later */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ #define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ #define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ @@ -313,7 +313,7 @@ /* 0x01800000 */ #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD100 | \ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index ac72f98..aca70dc 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -211,7 +211,7 @@ */ #define CFG_SDR_CONFIG 0x18 #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * FLASH and environment organization @@ -251,7 +251,7 @@ #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #else -#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 2ce39c9..c065d33 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -49,6 +49,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index fb5ae99..56b4d92 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -237,7 +237,7 @@ /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ #ifdef CONFIG_BOOT_ROOT_INITRD diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h new file mode 100644 index 0000000..622a5d4 --- /dev/null +++ b/include/configs/quad100hd.h @@ -0,0 +1,298 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * quad100hd.h - configuration for Quad100hd board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EP 1 /* Specifc 405EP support*/ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */ +#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */ + +/* the environment is in the EEPROM by default */ +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_IN_FLASH + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x01 /* PHY address */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_LOG +#undef CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#undef CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * SDRAM + *----------------------------------------------------------------------*/ +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 +#define CFG_SDRAM_SIZE 0x02000000 /* 32 MB */ + +/* FIX! SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/* + * JFFS2 + */ +#define CFG_JFFS2_FIRST_BANK 0 +#ifdef CFG_KERNEL_IN_JFFS2 +#define CFG_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */ +#else /* kernel not in JFFS */ +#define CFG_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */ +#endif +#define CFG_JFFS2_NUM_BANKS 1 + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */ + +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_SIZE 0x2000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (TEXT_BASE) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +/* the environment is located before u-boot */ +#define CFG_ENV_ADDR (TEXT_BASE - CFG_ENV_SECT_SIZE) + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) +#endif + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x400 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x00000000 +#define CFG_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */ +#endif + +/* partly from PPCBoot */ +/* NAND */ +#define CONFIG_NAND +#ifdef CONFIG_NAND +#define CFG_NAND_BASE 0x60000000 +#define CFG_NAND_CS 10 /* our CS is GPIO10 */ +#define CFG_NAND_RDY 23 /* our RDY is GPIO23 */ +#define CFG_NAND_CE 24 /* our CE is GPIO24 */ +#define CFG_NAND_CLE 31 /* our CLE is GPIO31 */ +#define CFG_NAND_ALE 30 /* our ALE is GPIO30 */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +/* see ./cpu/ppc4xx/start.S */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + * Taken from PPCBoot board/icecube/icecube.h + */ + +/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ +#define CFG_EBC_PB0AP 0x04002480 +/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */ +#define CFG_EBC_PB0CR 0xFFC5A000 +#define CFG_EBC_PB1AP 0x04005480 +#define CFG_EBC_PB1CR 0x60018000 +#define CFG_EBC_PB2AP 0x00000000 +#define CFG_EBC_PB2CR 0x00000000 +#define CFG_EBC_PB3AP 0x00000000 +#define CFG_EBC_PB3CR 0x00000000 +#define CFG_EBC_PB4AP 0x00000000 +#define CFG_EBC_PB4CR 0x00000000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * Taken in part from PPCBoot board/icecube/icecube.h + */ +/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ +#define CFG_GPIO0_OSRH 0x55555550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xFFFF8097 +#define CFG_GPIO0_ODR 0x00000000 + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* ENVIRONMENT VARS */ + +#define CONFIG_IPADDR 192.168.1.67 +#define CONFIG_SERVERIP 192.168.1.50 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_LOADADDR 300000 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 42787f4..4e89580 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -113,7 +113,7 @@ #define CFG_ENV_SECT_SIZE (16 * 1024) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_ERASE_TOUT 120000 #define CFG_FLASH_WRITE_TOUT 500 /* Board Clock */ diff --git a/include/configs/rmu.h b/include/configs/rmu.h index 2ca60b7..28fb7c3 100644 --- a/include/configs/rmu.h +++ b/include/configs/rmu.h @@ -51,9 +51,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -399,7 +399,7 @@ #define BCSR3 (CFG_BCSR_BASE + 3) #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h index 40a05fa..6251383 100644 --- a/include/configs/rsdproto.h +++ b/include/configs/rsdproto.h @@ -53,7 +53,7 @@ */ #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ +#undef CONFIG_CONS_NONE /* define if console on neither */ #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ /* @@ -91,7 +91,7 @@ #define CONFIG_ENV_OVERWRITE /* enable I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x30 @@ -128,7 +128,7 @@ #define CFG_RSD_BOOT_LOW 1 #define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs" +#define CONFIG_BOOTARGS "devfs=mount root=ramfs" #define CONFIG_ETHADDR 08:00:3e:26:0a:5a #define CONFIG_NETMASK 255.255.0.0 @@ -176,14 +176,14 @@ #define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ #define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ -#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ -#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ +#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ +#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ /*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ /*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ -#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ -#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ +#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ +#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ /*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ /*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index ec7d34a..4974fb4 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -441,7 +441,7 @@ /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ #ifdef CONFIG_BOOT_ROOT_INITRD diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index 9b05bd6..08cadf6 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -106,7 +106,9 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off" +#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \ + "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \ + "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off" #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.0.69 @@ -205,7 +207,7 @@ #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 6063398..7993137 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -387,7 +387,7 @@ /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ #ifdef CONFIG_BOOT_ROOT_INITRD diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 0ebc674..7481556 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -570,6 +570,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index c84b70a..358fc02 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -176,7 +176,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 20da73e..3cd9ff8 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -55,13 +55,13 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_NUM_DDR_CONTROLLERS 2 @@ -94,7 +94,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -219,7 +219,7 @@ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -236,14 +236,14 @@ #else #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ #endif -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -323,7 +323,7 @@ #undef CFG_SCSI_SCAN_BUS_REVERSE #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -331,7 +331,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -343,7 +343,7 @@ #define CONFIG_SATA_ULI5288 #define CFG_SCSI_MAX_SCSI_ID 4 #define CFG_SCSI_MAX_LUN 1 -#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE #endif @@ -352,7 +352,7 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif /* #define CONFIG_MII 1 */ /* MII PHY management */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 4df461d..0e830b8 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -87,7 +87,7 @@ #define CONFIG_CMD_EEPROM #define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index c6f7f15..051b2e0 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -88,8 +88,12 @@ #define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) " -#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm" +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 " \ + "mtdparts=phys:7936k(root),256k(uboot) " +#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf " \ + "console=ttyS0,9600 " \ + "mtdparts=phys:7808k(root),128k(env),256k(uboot);" \ + "bootp;bootm" #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 555316f..48251f3 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -318,7 +318,7 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ /* buffers & descriptors */ #define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ @@ -417,7 +417,7 @@ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ + /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -443,7 +443,7 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ /* CFG_PCI_MEMBASE */ /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT diff --git a/include/configs/shannon.h b/include/configs/shannon.h index c1fa53f..8bbc730 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -83,7 +83,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_BOOTCOMMAND "help" diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index 05f6053..ac1642e 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -114,17 +114,9 @@ #define CONFIG_BOOTDELAY 3 -#if 0 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#endif #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 134.98.93.36 #define CONFIG_SERVERIP 134.98.93.22 -#if 0 -#define CONFIG_BOOTFILE "elinos-lart" -#define CONFIG_BOOTCOMMAND "tftp; bootm" -#endif #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index 18a036c..efe4693 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -93,7 +93,7 @@ #define CONFIG_BOOTDELAY 3 -/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ +/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 10.0.0.110 diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 4578cae..3e47eb8 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h new file mode 100644 index 0000000..6dc9eff --- /dev/null +++ b/include/configs/socrates.h @@ -0,0 +1,423 @@ +/* + * (C) Copyright 2008 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * Wolfgang Denk <wd@denx.de> + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao <X.Xiao@motorola.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Socrates + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ +#define CONFIG_MPC8544 1 +#define CONFIG_SOCRATES 1 + +#define CONFIG_PCI + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ + +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66666666 +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 +#define CFG_MEMTEST_END 0x10000000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ + +/* Hardcoded values, to use instead of SPD */ +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG 0x80010102 +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x3935D322 +#define CFG_DDR_TIMING_2 0x14904CC8 +#define CFG_DDR_MODE 0x00480432 +#define CFG_DDR_INTERVAL 0x030C0100 +#define CFG_DDR_CONFIG_2 0x04400000 +#define CFG_DDR_CONFIG 0xC3008000 +#define CFG_DDR_CLK_CONTROL 0x03800000 +#define CFG_SDRAM_SIZE 256 /* in Megs */ + +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ +#define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */ +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +/* + * Flash on the Local Bus + */ +/* + * Flash on the LocalBus + */ +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ + +#define CFG_FLASH0 0xFE000000 +#define CFG_FLASH1 0xFC000000 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } + +#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ + +#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ + +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* I2C RTC */ +#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ + +/* I2C temp sensor */ +/* Socrates uses Maxim's DS75, which is compatible with LM75 */ +#define CONFIG_DTT_LM75 1 +#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 125 +#define CFG_DTT_LOW_TEMP -55 +#define CFG_DTT_HYSTERESIS 3 +#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Memory space is mapped 1-1. + */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + +/* PCI is clocked by the external source at 33 MHz */ +#define CONFIG_PCI_CLK_FREQ 33000000 +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xE2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#if defined(CONFIG_PCI) +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0,1] */ +#define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_TIMESTAMP /* Print image info with ts */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB + + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootfile=$hostname/uImage\0" \ + "netdev=eth0\0" \ + "consdev=ttyS0\0" \ + "hostname=socrates\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ + ":$hostname:$netdev:off panic=1\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=$hostname/socrates.dtb\0" \ + "fdt_addr_r=B00000\0" \ + "fdt_addr=FC1E0000\0" \ + "rootpath=/opt/eldk/ppc_85xx\0" \ + "kernel_addr=FC000000\0" \ + "kernel_addr_r=200000\0" \ + "ramdisk_addr=FC200000\0" \ + "ramdisk_addr_r=400000\0" \ + "load=tftp 100000 $hostname/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* USB support */ +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_PCI_OHCI 1 +#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CFG_OHCI_SWAP_REG_ACCESS 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_USB_STORAGE 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index b622a30..18f5533 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_SORCERY 1 /* Sorcery board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ @@ -189,7 +191,7 @@ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ CFG_FLASH_BASE+0x04000000 } /* two banks */ /* @@ -243,12 +245,12 @@ /* SDRAM configuration (for SPD) */ #define CFG_SDRAM_TOTAL_BANKS 1 -#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ +#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ #define CFG_SDRAM_SPD_SIZE 0x100 -#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ +#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ /* SDRAM drive strength register (for SSTL_2 class II)*/ -#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ +#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ @@ -285,7 +287,7 @@ #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ #if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 49213dc..69d2d67 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -44,6 +44,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index fc5d0cc..ec04a30 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -42,8 +42,8 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support*/ +#undef CONFIG_PCI /* pci ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support*/ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ @@ -100,7 +100,7 @@ #define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ #define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -109,9 +109,9 @@ #endif #ifdef CFG_RAMBOOT -#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ +#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ #else -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ @@ -129,14 +129,14 @@ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ +#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ #undef CONFIG_CLOCKS_IN_MHZ /* local bus definitions */ #define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ +#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ #define CFG_LBC_LBCR 0x00000000 #define CFG_LBC_LSRT 0x20000000 #define CFG_LBC_MRTPR 0x20000000 @@ -147,23 +147,23 @@ #define CFG_LBC_LSDMR_5 0x4061b723 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} @@ -205,18 +205,18 @@ #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */ -#if defined(CONFIG_PCI) /* PCI Ethernet card */ +#if defined(CONFIG_PCI) /* PCI Ethernet card */ #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW @@ -227,7 +227,7 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -270,7 +270,7 @@ #elif (CONFIG_ETHER_INDEX == 3) /* need more definitions here for FE3 */ #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ +#endif /* CONFIG_ETHER_INDEX */ /* MDIO is done through the TSEC0 control. */ @@ -375,20 +375,20 @@ /*Note: change below for your network setting!!! */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a +#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b +#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c +#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c #endif -#define CONFIG_SERVERIP 192.168.85.1 -#define CONFIG_IPADDR 192.168.85.60 +#define CONFIG_SERVERIP 192.168.85.1 +#define CONFIG_IPADDR 192.168.85.60 #define CONFIG_GATEWAYIP 192.168.85.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME STX_GP3 -#define CONFIG_ROOTPATH /gppproot -#define CONFIG_BOOTFILE uImage +#define CONFIG_HOSTNAME STX_GP3 +#define CONFIG_ROOTPATH /gppproot +#define CONFIG_BOOTFILE uImage #define CONFIG_LOADADDR 0x1000000 #endif /* __CONFIG_H */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 15f690a..d033c86 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -69,10 +69,10 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 @@ -232,7 +232,7 @@ #define CFG_PCI2_IO_PHYS 0xe3000000 #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ -#if defined(CONFIG_PCI) /* PCI Ethernet card */ +#if defined(CONFIG_PCI) /* PCI Ethernet card */ #define CONFIG_MPC85XX_PCI2 1 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -428,13 +428,13 @@ #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ #define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate" -#define CONFIG_SERVERIP 192.168.85.1 +#define CONFIG_SERVERIP 192.168.85.1 #define CONFIG_IPADDR 192.168.85.60 #define CONFIG_GATEWAYIP 192.168.85.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME STX_SSA -#define CONFIG_ROOTPATH /gppproot -#define CONFIG_BOOTFILE uImage +#define CONFIG_HOSTNAME STX_SSA +#define CONFIG_ROOTPATH /gppproot +#define CONFIG_BOOTFILE uImage #define CONFIG_LOADADDR 0x1000000 #else /* ENV IS IN FLASH -- use a full-blown envionment */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index a3ab798..97a1032 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -63,9 +63,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_AUTOSCRIPT @@ -93,7 +93,7 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 @@ -101,7 +101,7 @@ #undef CONFIG_RMII #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ +#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ #undef CONFIG_FEC1_PHY_NORXERR #define CONFIG_ETHER_ON_FEC2 1 @@ -214,7 +214,7 @@ #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 -#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -283,11 +283,11 @@ #if MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 66666666 #define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -462,7 +462,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 3b90f3c..70336b5 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -68,7 +68,7 @@ #undef CONFIG_WATCHDOG /* watchdog */ -#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ +#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ #ifdef CONFIG_LCD /* with LCD controller ? */ /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ @@ -109,8 +109,8 @@ "ramdisk_addr=48100000\0" \ "" #define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -363,14 +363,14 @@ *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ #define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ #define CFG_ATA_BASE_ADDR 0xFE100010 #define CFG_ATA_IDE0_OFFSET 0x0000 diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 8a1ff1a..c060b1e 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -363,7 +363,7 @@ unsigned char spi_read(void); { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \ { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \ { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \ diff --git a/include/configs/trab.h b/include/configs/trab.h index b9088a8..de36fca 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -69,8 +69,8 @@ * address 0x54 with 8bit addressing ***********************************************************/ #define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ #define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM address */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */ @@ -237,7 +237,7 @@ "mdm_init2=ATS0=1\0" \ "mdm_flow_control=rts/cts\0" #endif /* CFG_HUSH_PARSER */ -#else /* CONFIG_FLASH_8MB => 8 MB flash */ +#else /* CONFIG_FLASH_8MB => 8 MB flash */ #ifdef CFG_HUSH_PARSER #define CONFIG_EXTRA_ENV_SETTINGS \ "nfs_args=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 7a15d97..25155ad 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -303,7 +303,7 @@ #define CFG_MONITOR_LEN 0x40000 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ @@ -314,8 +314,8 @@ /* Flash environment locations */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h index 3c2de40..e74b1bb 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -243,7 +243,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN) -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index dc1d7e1..042750e 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index cd00c49..287a618 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -58,7 +58,7 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" #define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ #define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ @@ -255,7 +255,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" mem_freq = 100MHz */ #define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ -#define CFG_BANK6_ROW 0 /* bit count */ +#define CFG_BANK6_ROW 0 /* bit count */ #define CFG_BANK5_ROW 0 #define CFG_BANK4_ROW 0 #define CFG_BANK3_ROW 0 @@ -278,7 +278,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" #define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ -#define CFG_ACTORW 2 /* trcd min */ +#define CFG_ACTORW 2 /* trcd min */ #define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ #define CFG_REGISTERD_TYPE_BUFFER 1 #define CFG_EXTROM 0 /* we don't need extended ROM space */ diff --git a/include/configs/v37.h b/include/configs/v37.h index 47851c2..751d702 100644 --- a/include/configs/v37.h +++ b/include/configs/v37.h @@ -34,7 +34,7 @@ */ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_V37 1 /* ...on a Marel V37 board */ +#define CONFIG_V37 1 /* ...on a Marel V37 board */ #define CONFIG_LCD #define CONFIG_SHARP_LQ084V1DG21 @@ -63,10 +63,10 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ + "tftpboot; " \ "setenv bootargs console=tty0 " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -333,7 +333,7 @@ #define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ -#define CFG_OR_TIMING_FLASH 0xF56 +#define CFG_OR_TIMING_FLASH 0xF56 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V) diff --git a/include/configs/v38b.h b/include/configs/v38b.h index e24d6f7..c203522 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -46,6 +46,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/versatile.h b/include/configs/versatile.h index d250150..a88d356 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -80,7 +80,7 @@ #define CONFIG_DRIVER_SMC91111 #define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0x10010000 +#define CONFIG_SMC91111_BASE 0x10010000 #undef CONFIG_SMC91111_EXT_PHY /* diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index c67b301..f2efe9f 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -132,9 +132,9 @@ /* * Configuration for FLASH memory */ -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ -#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ +#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ #define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ #define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ #define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 7418986..dc0ee0b2 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -97,7 +97,7 @@ #define CONFIG_BOOTCOMMAND "bootm 0x00100000" #define CONFIG_BOOTARGS "console=ttyS1,115200" #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index c738567..570d6a8 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -124,7 +124,7 @@ * 0x3FFB_F000 CFG_MONITOR_BASE * MONITOR_CODE 256kB Env * 0x3FFF_F000 CFG_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd + * GLOBAL_DATA 4kB bd, gd * 0x4000_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE */ @@ -194,13 +194,13 @@ #define CFG_LONGHELP #define CFG_LOAD_ADDR 0x12000000 /* default load address */ -#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME "xupv2p" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.5 +#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD /* architecture dependent code */ |