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| author | Kumar Gala <galak@kernel.crashing.org> | 2010-12-30 12:09:53 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:21 -0600 |
| commit | a09b9b68d492e978ef0e14cae93ff9cfbc2d3e4b (patch) | |
| tree | 07f0d677a4d7ac227abc90cdbbd90d306641f76e /include/configs | |
| parent | 213ac73e2caff8b477c31f85d8132f8cc116f366 (diff) | |
| download | u-boot-imx-a09b9b68d492e978ef0e14cae93ff9cfbc2d3e4b.zip u-boot-imx-a09b9b68d492e978ef0e14cae93ff9cfbc2d3e4b.tar.gz u-boot-imx-a09b9b68d492e978ef0e14cae93ff9cfbc2d3e4b.tar.bz2 | |
powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe
controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/corenet_ds.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e1cd1b0..d1ac756 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,6 +51,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ @@ -265,21 +266,21 @@ /* * RapidIO */ -#define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * General PCI |