Merge with /home/wd/git/u-boot/master

17 files changed, 2688 insertions, 142 deletions

diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 9a98e5c..7a1dada 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -455,7 +455,7 @@
 #define CFG_MIN_AM_MASK 0xC0000000
 
 /*
- * we use the same values for 32 MB and 128 MB SDRAM
+ * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
  * refresh rate = 7.68 uS (100 MHz Bus Clock)
  */
 
@@ -510,6 +510,24 @@
 			 PSDMR_WRC_1C			|\
 			 PSDMR_CL_2)
 
+	/* SDRAM initialization values for 10-column chips
+	 */
+#define CFG_OR2_10COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A4		|\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_10COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A17_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI1_A6		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+			 
 /*
  * Init Memory Controller:
  *
@@ -588,9 +606,9 @@
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	 CFG_OR2_9COL
+#define CFG_OR2_PRELIM	 CFG_OR2_8COL
 
-#define CFG_PSDMR	 CFG_PSDMR_9COL
+#define CFG_PSDMR	 CFG_PSDMR_8COL
 #endif /* CFG_RAMBOOT */
 
 /* Bank 3 - Dual Ported SRAM
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
new file mode 100644
index 0000000..8a6e5a6
--- /dev/null
+++ b/include/configs/TB5200.h
@@ -0,0 +1,507 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
+#define CONFIG_TB5200		1	/* ... on a TB5200 base board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* default console is on PSC1 */
+#define CONFIG_SERIAL_MULTI	1	/* support multiple consoles */
+#define CONFIG_PSC_CONSOLE2	6	/* second console is on PSC6 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_VIDEO
+#define ADD_BMP_CMD		CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD		0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CPU	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* IDE */
+#define ADD_IDE_CMD		(CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				ADD_BMP_CMD	| \
+				ADD_IDE_CMD	| \
+				ADD_PCI_CMD	| \
+				ADD_USB_CMD	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_POST_DIAG | \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SNTP	| \
+				CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#if defined(CONFIG_TQM5200_B)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	"update=protect off FC000000 FC07FFFF;"				\
+		"erase FC000000 FC07FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC07FFFF\0"			\
+	""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 $(u-boot)\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+#endif /* CONFIG_TQM5200_B */
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #2 */
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* List of I2C addresses to be verified by POST */
+#undef I2C_ADDR_LIST
+#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
+				CFG_I2C_RTC_ADDR,	\
+				CFG_I2C_SLAVE }
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE	1
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CFG_LOWBOOT */
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00080000)
+#else
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+#endif /* CONFIG_TQM5200_B */
+#endif	/* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
+#if defined(CONFIG_TQM5200_B)
+#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
+						"1280k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"16m(big-fs),"		\
+						"8m(misc)"
+#else
+#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
+						"1408k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"16m(big-fs),"		\
+						"8m(misc)"
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_SECT_SIZE	0x40000
+#else
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#if defined(CONFIG_TQM5200_B)
+#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#endif /* CONFIG_TQM5200_B */
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *	Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *	      (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *	000 -> All PSC2 pins are GIOPs
+ *	001 -> CAN1/2 on PSC2 pins
+ *	       Use for REV100 STK52xx boards
+ * use PSC3: Bits 20:23 (mask: 0x00000300):
+ *      0001 -> USB2
+ *      0000 -> GPIO
+ * use PSC6:
+ *   on STK52xx:
+ *	use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *	Bits 9:11 (mask: 0x00700000):
+ *	   101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#define CFG_GPS_PORT_CONFIG	0x81500114
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_M41T11	1
+#define CFG_I2C_RTC_ADDR	0x68
+#define CFG_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
+					   year */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CFG_CS2_START		0xE5000000
+#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
+#define CFG_CS2_CFG		0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE		0xE0000000
+#define CFG_CS1_START		(SM501_FB_BASE)
+#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CFG_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 6b8759f..be83b67 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -2,7 +2,7 @@
  * (C) Copyright 2003-2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2005
+ * (C) Copyright 2004-2006
  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  *
  * See file CREDITS for list of people who contributed to this
@@ -32,27 +32,30 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
-#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
-#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
-#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
+#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#ifndef CONFIG_CAM5200			/* On a Cameron board or ...		*/
+#define CONFIG_STK52XX		1	/* ... on a STK52XX board		*/
+#endif
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
 
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
  * Serial console configuration
  */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps			*/
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #ifdef CONFIG_STK52XX
@@ -96,7 +99,7 @@
 /*
  * Video console
  */
-#if 1
+#ifndef CONFIG_TQM5200S		/* No graphics controller on TQM5200S */
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_SM501
 #define CONFIG_VIDEO_SM501_32BPP
@@ -129,10 +132,12 @@
 #define ADD_USB_CMD		0
 #endif
 
+#ifndef CONFIG_CAM5200
 /* POST support */
 #define CONFIG_POST		(CFG_POST_MEMORY   | \
 				 CFG_POST_CPU	   | \
 				 CFG_POST_I2C)
+#endif
 
 #ifdef CONFIG_POST
 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
@@ -176,8 +181,8 @@
 
 #define	CONFIG_TIMESTAMP		/* display image timestamps */
 
-#if (TEXT_BASE == 0xFC000000)		/* Boot low */
-#   define CFG_LOWBOOT		1
+#if (TEXT_BASE != 0xFFF00000)
+#   define CFG_LOWBOOT		1	/* Boot low */
 #endif
 
 /*
@@ -186,11 +191,43 @@
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;" \
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 
 #undef	CONFIG_BOOTARGS
 
+#ifdef CONFIG_STK52XX
+# if defined(CONFIG_TQM5200_B)
+#  if defined(CFG_LOWBOOT)
+#   define ENV_UPDT							\
+	"update=protect off FC000000 FC07FFFF;"				\
+		"erase FC000000 FC07FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC07FFFF\0"
+#  else	/* highboot */
+#   define ENV_UPDT							\
+	"update=protect off FFF00000 FFF7FFFF;"				\
+		"erase FFF00000 FFF7FFFF;"				\
+		"cp.b 200000 FFF00000 ${filesize};"			\
+		"protect on FFF00000 FFF7FFFF\0"
+#  endif /* CFG_LOWBOOT */
+# else	/* !CONFIG_TQM5200_B */
+#  define ENV_UPDT							\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"
+# endif /* CONFIG_TQM5200_B */
+#elif defined (CONFIG_CAM5200)
+#   define ENV_UPDT							\
+	"update=protect off FC000000 FC03FFFF;"				\
+		"erase FC000000 FC03FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC03FFFF\0"
+#else
+# error "Unknown Carrier Board"
+#endif	/* CONFIG_STK52XX */
+
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
@@ -200,18 +237,18 @@
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_self=run ramargs addip;"					\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate}\0"				\
+	"flash_self=run ramargs addip addcons;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs=run nfsargs addip;"					\
+	"flash_nfs=run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
+		"bootm\0"						\
 	"bootfile=/tftpboot/tqm5200/uImage\0"				\
-	"load=tftp 200000 ${u-boot}\0"					\
 	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
-	"update=protect off FC000000 FC05FFFF;"				\
-		"erase FC000000 FC05FFFF;"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC05FFFF\0"			\
+	"load=tftp 200000 ${u-boot}\0"					\
+	ENV_UPDT							\
 	""
 
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
@@ -283,45 +320,80 @@
 /*
  * Flash configuration
  */
-#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+#define CFG_FLASH_BASE		0xFC000000
 
-/* use CFI flash driver if no module variant is spezified */
+/* use CFI flash driver */
 #define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
 #define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
 #define CFG_FLASH_EMPTY_INFO
 #define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
 #define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+#define CFG_FLASH_USE_BUFFER_WRITE	1
+
+#if defined (CONFIG_CAM5200)
+# define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+#elif defined(CONFIG_TQM5200_B)
+# define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00080000)
+#else
+# define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+#endif
 
-#if !defined(CFG_LOWBOOT)
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else	/* CFG_LOWBOOT */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
-#endif	/* CFG_LOWBOOT */
 #define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
 
 /* Dynamic MTD partition support */
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
-#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
+
+#ifdef CONFIG_STK52XX
+# if defined(CONFIG_TQM5200_B)
+#  if defined(CFG_LOWBOOT)
+#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:1m(firmware),"	\
+						"1536k(kernel),"	\
+						"3584k(small-fs),"	\
+						"2m(initrd),"		\
+						"8m(misc),"		\
+						"16m(big-fs)"
+#  else	/* highboot */
+#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:2560k(kernel),"	\
+						"3584k(small-fs),"	\
+						"2m(initrd),"		\
+						"8m(misc),"		\
+						"15m(big-fs),"		\
+						"1m(firmware)"
+#  endif /* CFG_LOWBOOT */
+# else	/* !CONFIG_TQM5200_B */
+#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
 						"1408k(kernel),"	\
 						"2m(initrd),"		\
 						"4m(small-fs),"		\
-						"16m(big-fs),"		\
-						"8m(misc)"
+						"8m(misc),"		\
+						"16m(big-fs)"
+# endif /* CONFIG_TQM5200_B */
+#elif defined (CONFIG_CAM5200)
+#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
+						"1792k(kernel),"	\
+						"3584k(small-fs),"	\
+						"2m(initrd),"		\
+						"8m(misc),"		\
+						"16m(big-fs)"
+#else
+# error "Unknown Carrier Board"
+#endif	/* CONFIG_STK52XX */
 
 /*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SIZE		0x4000	/* 16 k - keep small for fast booting */
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_SECT_SIZE	0x40000
+#else
 #define CFG_ENV_SECT_SIZE	0x20000
+#endif /* CONFIG_TQM5200_B */
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
 /*
  * Memory map
@@ -349,8 +421,15 @@
 #   define CFG_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#if defined (CONFIG_CAM5200)
+# define CFG_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#elif defined(CONFIG_TQM5200_B)
+# define CFG_MONITOR_LEN	(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+# define CFG_MONITOR_LEN	(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#endif
+
+#define CFG_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
@@ -411,6 +490,8 @@
 #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
 # define CONFIG_RTC_M41T11 1
 # define CFG_I2C_RTC_ADDR 0x68
+# define CFG_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
+					   year */
 #else
 # define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
 #endif
@@ -420,6 +501,10 @@
  */
 #define CFG_LONGHELP			/* undef to save memory	    */
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define	CFG_PROMPT_HUSH_PS2	"> "
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -466,32 +551,25 @@
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE
 
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
 #define CONFIG_LAST_STAGE_INIT
-#endif
 
 /*
  * SRAM - Do not map below 2 GB in address space, because this area is used
  * for SDRAM autosizing.
  */
-#if defined (CONFIG_CS_AUTOCONF)
 #define CFG_CS2_START		0xE5000000
 #define CFG_CS2_SIZE		0x100000	/* 1 MByte */
 #define CFG_CS2_CFG		0x0004D930
-#endif
 
 /*
  * Grafic controller - Do not map below 2 GB in address space, because this
  * area is used for SDRAM autosizing.
  */
-#if defined (CONFIG_CS_AUTOCONF)
 #define SM501_FB_BASE		0xE0000000
 #define CFG_CS1_START		(SM501_FB_BASE)
 #define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
 #define CFG_CS1_CFG		0x8F48FF70
 #define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
-#endif
 
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index da6946b..780f274 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -158,7 +158,7 @@
 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 
-#else
+#else	/* ! TQM8560 */
 
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
@@ -170,19 +170,21 @@
 #define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
 #define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
 
-#endif /* CONFIG_TQM8560 */
-
-#define CONFIG_BAUDRATE         115200
-
-#define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
 /* PS/2 Keyboard */
+#if !defined(CONFIG_TQM8560)
 #define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
 #define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
 #define CONFIG_PS2SERIAL	2	/* .. on DUART2			*/
 #define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
 #define CONFIG_BOARD_EARLY_INIT_R	1
+#endif /* !CONFIG_TQM8560 */
+
+#endif /* CONFIG_TQM8560 */
+
+#define CONFIG_BAUDRATE         115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
new file mode 100644
index 0000000..ede4e3b
--- /dev/null
+++ b/include/configs/TQM885D.h
@@ -0,0 +1,492 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
+#define CONFIG_TQM885D		1	/* ...on a TQM88D module	*/
+
+#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
+#define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  50 MHz - CPU default clock	*/
+						/* (it will be used if there is no	*/
+						/* 'cpuclk' variable with valid value)	*/
+
+#define CFG_MEASURE_CPUCLK			/* Measure real cpu clock	*/
+						/* (function measure_gclk()	*/
+						/* will be called)		*/
+#ifdef CFG_MEASURE_CPUCLK
+#define CFG_8XX_XIN		10000000	/* measure_gclk() needs this	*/
+#endif
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM866M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+# define CONFIG_RTC_DS1337 1
+# define CFG_I2C_RTC_ADDR 0x68
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/
+
+#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
+#define CFG_ALT_MEMTEST				/* alternate, more extensive
+						   memory test.*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+				 OR_SCY_6_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * 4096	Rows from SDRAM example configuration
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Memory Periodic Timer Prescaler
+ * Periodic timer for refresh, start with refresh rate for 40 MHz clock
+ * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ */
+#define CFG_MAMR_PTA		39
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Network configuration
+ */
+#define CONFIG_SCC2_ENET		/* enable ethernet on SCC2 */
+#define CONFIG_FEC_ENET			/* enable ethernet on FEC */
+#define CONFIG_ETHER_ON_FEC1		/* ... for FEC1 */
+#define CONFIG_ETHER_ON_FEC2		/* ... for FEC2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_NET_RETRY_COUNT 1	/* reduce max. timeout before
+					   switching to another netwok (if the
+					   tried network is unreachable) */
+
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/aev.h b/include/configs/aev.h
index aa6bc91..8d9f0a1 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2004-2005
@@ -370,10 +370,7 @@
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE
 
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
 #define CONFIG_LAST_STAGE_INIT
-#endif
 
 /*
  * SRAM - Do not map below 2 GB in address space, because this area is used
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 6d32821..2c1c319 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -49,7 +49,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
 #define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
 #define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
@@ -257,8 +257,8 @@
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
 	"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0"		\
-	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
-		"cp.b 100000 fff80000 80000;"			        \
+	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
+		"cp.b 100000 fffa0000 60000;"			        \
 		"setenv filesize;saveenv\0"				\
 	"upd=run load;run update\0"					\
 	""
@@ -358,6 +358,14 @@
 
 #define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#else
+#define CONFIG_AUTO_COMPLETE
+#endif
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index 77d2d56..a49ed3b 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -34,7 +34,7 @@
 
 #define CONFIG_AU1000		1
 
-#define CONFIG_MISC_INIT_R      1
+#define CONFIG_MISC_INIT_R	1
 
 #define CONFIG_ETHADDR		DE:AD:BE:EF:01:02    /* Ethernet address */
 
@@ -59,21 +59,21 @@
 #define CONFIG_AUTOBOOT_DELAY_STR "d"
 #define CONFIG_AUTOBOOT_STOP_STR " "
 
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-#define	CONFIG_BOOTARGS "panic=1"
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#define CONFIG_BOOTARGS "panic=1"
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	"addmisc=setenv bootargs $(bootargs) "				\
-	        "ethaddr=$(ethaddr) \0"					\
-        "netboot=bootp;run addmisc;bootm\0"                             \
-                ""
+		"ethaddr=$(ethaddr) \0"					\
+	"netboot=bootp;run addmisc;bootm\0"				\
+		""
 
 /* Boot from Compact flash partition 2 as default */
 #define CONFIG_BOOTCOMMAND	"ide reset;disk 0x81000000 0:2;run addmisc;bootm"
 
-#define CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
  ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
-   CFG_CMD_MII | CFG_CMD_LOADS  | CFG_CMD_LOADB | CFG_CMD_ELF | \
+   CFG_CMD_MII | CFG_CMD_LOADS	| CFG_CMD_LOADB | CFG_CMD_ELF | \
    CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
 
 #include <cmd_confdefs.h>
@@ -81,11 +81,11 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP				/* undef to save memory      */
-#define	CFG_PROMPT		"GTH2 # "	/* Monitor Command Prompt    */
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args*/
+#define CFG_LONGHELP				/* undef to save memory	     */
+#define CFG_PROMPT		"GTH2 # "	/* Monitor Command Prompt    */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args*/
 
 #define CFG_MALLOC_LEN		128*1024
 
@@ -93,16 +93,16 @@
 
 #define CFG_MHZ			500
 
-#define CFG_HZ                  (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_HZ			(CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
 
-#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+#define CFG_LOAD_ADDR		0x81000000     /* default load address	*/
 
 #define CFG_MEMTEST_START	0x80100000
 #define CFG_MEMTEST_END		0x83000000
 
-#define CONFIG_HW_WATCHDOG      1
+#define CONFIG_HW_WATCHDOG	1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
@@ -113,8 +113,8 @@
 #define PHYS_FLASH		0xbfc00000 /* Flash Bank #1 */
 
 /* The following #defines are needed to get flash environment right */
-#define	CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(192 << 10)
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)
 
 #define CFG_INIT_SP_OFFSET	0x400000
 
@@ -125,7 +125,7 @@
 #define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
 
-#define	CFG_ENV_IS_NOWHERE	1
+#define CFG_ENV_IS_NOWHERE	1
 
 /* Address and size of Primary Environment Sector	*/
 #define CFG_ENV_ADDR		0xB0030000
@@ -158,21 +158,21 @@
 #define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
 #define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
 #define CFG_ATA_IDE0_OFFSET	0
 
-#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_IO_BASE
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_IO_BASE
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET     0
+#define CFG_ATA_DATA_OFFSET	0
 
-/* Offset for normal register accesses  */
-#define CFG_ATA_REG_OFFSET      0
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0
 
-/* Offset for alternate registers       */
-#define CFG_ATA_ALT_OFFSET      0x0200
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0200
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
new file mode 100644
index 0000000..61cf705
--- /dev/null
+++ b/include/configs/kvme080.h
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_KVME080		1
+
+#define CONFIG_CONS_INDEX	1
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.0.1
+
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,115200 " \
+	"root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
+	"ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
+	"kvme080:eth0:none " \
+	"mtdparts=phys_mapped_flash:12m(root),-(kernel)"
+
+#define CONFIG_BOOTCOMMAND \
+	"tftp 800000 kvme080/uImage; " \
+	"bootm 800000"
+
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_LOADS_ECHO	1
+#undef	CFG_LOADS_BAUD_CHANGE
+
+#undef	CONFIG_WATCHDOG
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_DS164x
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
+				  CFG_CMD_ASKENV	| \
+				  CFG_CMD_CACHE		| \
+				  CFG_CMD_DATE		| \
+				  CFG_CMD_DHCP		| \
+				  CFG_CMD_DIAG		| \
+				  CFG_CMD_EEPROM	| \
+				  CFG_CMD_ELF		| \
+				  CFG_CMD_I2C		| \
+				  CFG_CMD_JFFS2		| \
+				  CFG_CMD_NFS		| \
+				  CFG_CMD_PCI		| \
+				  CFG_CMD_PING		| \
+				  CFG_CMD_SDRAM		| \
+				  CFG_CMD_SNTP)
+
+#define CONFIG_NETCONSOLE
+
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16
+#define CFG_BARGSIZE		CFG_CBSIZE
+
+#define CFG_MEMTEST_START	0x00400000
+#define CFG_MEMTEST_END		0x07C00000
+
+#define CFG_LOAD_ADDR		0x00100000
+#define CFG_HZ			1000
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x7C000000
+#define CFG_EUMB_ADDR		0xFC000000
+#define CFG_NVRAM_BASE_ADDR	0xFF000000
+#define CFG_NS16550_COM1	0xFF080000
+#define CFG_NS16550_COM2	0xFF080010
+#define CFG_NS16550_COM3	0xFF080020
+#define CFG_NS16550_COM4	0xFF080030
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#define CFG_MAX_RAM_SIZE	0x20000000
+#define CFG_FLASH_SIZE		(16 * 1024 * 1024)
+#define CFG_NVRAM_SIZE		0x7FFF8
+
+#define CONFIG_VERY_BIG_RAM
+
+#define CFG_MONITOR_LEN		0x00040000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_LEN		(512 << 10)
+
+#define CFG_BOOTMAPSZ		(8 << 20)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_PROTECTION
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_PROTECT_CLEAR
+
+#define CFG_MAX_FLASH_BANKS	1
+#define CFG_MAX_FLASH_SECT	256
+
+#define CFG_FLASH_ERASE_TOUT	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+
+#define CFG_ENV_IS_IN_NVRAM	1
+#define CONFIG_ENV_OVERWRITE	1
+#define CFG_NVRAM_ACCESS_ROUTINE
+#define CFG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
+#define CFG_ENV_SIZE		0x400
+#define CFG_ENV_OFFSET		0
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		14745600
+
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define CFG_RX_ETH_BUFFER	8
+
+#define CONFIG_HARD_I2C		1
+#define CFG_I2C_SPEED		400000
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR		0x57
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_SYS_CLK_FREQ	33333333
+
+#define CFG_CACHELINE_SIZE	32
+#if CONFIG_COMMANDS & CFG_CMD_KGDB
+#  define CFG_CACHELINE_SHIFT	5
+#endif
+
+#define CFG_DLL_EXTEND		0x00
+#define CFG_PCI_HOLD_DEL	0x20
+
+#define CFG_ROMNAL		15
+#define CFG_ROMFAL		31
+
+#define CFG_REFINT		430
+
+#define CFG_DBUS_SIZE2		1
+
+#define CFG_BSTOPRE		121
+#define CFG_REFREC		8
+#define CFG_RDLAT		4
+#define CFG_PRETOACT		3
+#define CFG_ACTTOPRE		5
+#define CFG_ACTORW		3
+#define CFG_SDMODE_CAS_LAT	3
+#define CFG_SDMODE_WRAP		0
+
+#define CFG_REGISTERD_TYPE_BUFFER	1
+#define CFG_EXTROM			1
+#define CFG_REGDIMM			0
+
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(0x4000000 - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x04000000
+#define CFG_BANK1_END		(0x8000000 - 1)
+#define CFG_BANK1_ENABLE	1
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+
+#define CFG_BANK_ENABLE		0x03
+
+#define CFG_ODCR		0x75
+#define CFG_PGMAX		0x32
+
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+#define BOOTFLAG_COLD	0x01
+#define BOOTFLAG_WARM	0x02
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index d8d63a1..ce33b85 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -47,8 +47,22 @@
 
 /*
  * Serial console configuration
+ *
+ *  To select console on the one of 8 external UARTs,
+ * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
+ * or as 5, 6, 7, or 8 for the second Quad UART.
+ *
+ *  CONFIG_PSC_CONSOLE must be undefined in this case.
+ */
+/* #define CONFIG_QUART_CONSOLE	1	*/ /* console is on UART1 of QUART1	*/
+/*
+ *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
+ * and undefine CONFIG_QUART_CONSOLE.
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
+#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
+#error "Select only one console device!"
+#endif
 #define CONFIG_BAUDRATE		115200
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
@@ -256,11 +270,59 @@
 #define CFG_CS2_SIZE		0x00001000
 #define CFG_CS2_CFG		0x1d300
 
+/* Second Quad UART @0x80010000 */
+#define CFG_CS1_START		0x80010000
+#define CFG_CS1_SIZE		0x00001000
+#define CFG_CS1_CFG		0x1d300
+
+/*
+ *  Select one of quarts as a default
+ * console. If undefined - PSC console
+ * wil be default
+ */
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333333
 
 #define CFG_RESET_ADDRESS	0xff000000
 
+/*
+ * QUART Expanders support
+ */
+#if defined(CONFIG_QUART_CONSOLE)
+/*
+ * We'll use NS16550 chip routines,
+ */
+#define CFG_NS16550		1
+#define CFG_NS16550_SERIAL	1
+#define CONFIG_CONS_INDEX	1
+/*
+ *  To achieve necessary offset on SC16C554
+ * A0-A2 (register select) pins with NS16550
+ * functions (in struct NS16550), REG_SIZE
+ * should be 4, because A0-A2 pins are connected
+ * to DA2-DA4 address bus lines.
+ */
+#define CFG_NS16550_REG_SIZE	4
+/*
+ * LocalPlus Bus already inited in cpu_init_f(),
+ * so can work with QUART's chip selects.
+ * One of four SC16C554 UARTs is selected with
+ * A3-A4 (DA5-DA6) lines.
+ */
+#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
+#define CFG_NS16550_COM1	(CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
+#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
+#define CFG_NS16550_COM1	(CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
+#elif
+#error "Wrong QUART expander number."
+#endif
+
+/*
+ * SC16C554 chip's external crystal oscillator frequency
+ * is 7.3728 MHz
+ */
+#define CFG_NS16550_CLK		7372800
+#endif /* CONFIG_QUART_CONSOLE */
 /*-----------------------------------------------------------------------
  * USB stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index ea15524..072b9dd 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -1,9 +1,9 @@
 /*
  * ppmc7xx.h
  * ---------
- * 
+ *
  * Wind River PPMC 7xx/74xx board configuration file.
- * 
+ *
  * By Richard Danter (richard.danter@windriver.com)
  * Copyright (C) 2005 Wind River Systems
  */
@@ -16,15 +16,15 @@
 
 
 /*===================================================================
- * 
+ *
  * User configurable settings - Modify to your preference
- * 
+ *
  *===================================================================
  */
 
 /*
  * Debug
- * 
+ *
  * DEBUG			- Define this is you want extra debug info
  * GTREGREAD			- Required to build with debug
  * do_bdinfo			- Required to build with debug
@@ -37,7 +37,7 @@
 
 /*
  * CPU type
- * 
+ *
  * CONFIG_7xx			- We have a 750 or 755 CPU
  * CONFIG_74xx			- We have a 7400 CPU
  * CONFIG_ALTIVEC		- We have altivec enabled CPU (only 7400)
@@ -52,11 +52,11 @@
 
 /*
  * Monitor configuration
- * 
+ *
  * CONFIG_COMMANDS		- List of command sets to include in shell
- * 
+ *
  * The following command sets have been tested and known to work:
- * 
+ *
  * CFG_CMD_CACHE		- Cache control commands
  * CFG_CMD_MEMORY		- Memory display, change and test commands
  * CFG_CMD_FLASH		- Erase and program flash
@@ -91,7 +91,7 @@
 
 /*
  * PCI config
- * 
+ *
  * CONFIG_PCI				- Enable PCI bus
  * CONFIG_PCI_PNP			- Enable Plug & Play support
  * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
@@ -104,7 +104,7 @@
 
 /*
  * Network config
- * 
+ *
  * CONFIG_NET_MULTI			- Support for multiple network interfaces
  * CONFIG_EEPRO100			- Intel 8255x Ethernet Controller
  * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
@@ -117,18 +117,18 @@
 
 /*
  * Enable extra init functions
- * 
+ *
  * CONFIG_MISC_INIT_F		- Call pre-relocation init functions
  * CONFIG_MISC_INIT_R		- Call post relocation init functions
  */
 
 #undef	CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R 
+#define CONFIG_MISC_INIT_R
 
 
 /*
  * Boot config
- * 
+ *
  * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
  * CONFIG_BOOTDELAY			- How long to wait before auto-boot (in sec)
  */
@@ -142,9 +142,9 @@
 
 
 /*===================================================================
- * 
+ *
  * Board configuration settings - You should not need to modify these
- * 
+ *
  *===================================================================
  */
 
@@ -154,9 +154,9 @@
 
 /*
  * Memory map
- * 
+ *
  * This board runs in a standard CHRP (Map-B) configuration.
- * 
+ *
  *	Type		Start		End			Size	Width	Chip Sel
  *	----------- ----------- ----------- ------- ------- --------
  *	SDRAM		0x00000000	0x04000000	64MB	64b		SDRAMCS0
@@ -164,9 +164,9 @@
  *	UART		0x7C000000						RCS2
  *	Mailbox		0xFF000000						RCS1
  *	Flash		0xFFC00000	0xFFFFFFFF	4MB	64b		RCS0
- * 
+ *
  * Flash sectors are laid out as follows.
- * 
+ *
  *	Sector	Start		End			Size	Comments
  *	------- ----------- ----------- ------- -----------
  *	 0		0xFFC00000	0xFFC3FFFF	256KB
@@ -193,7 +193,7 @@
 
 /*
  * SDRAM config - see memory map details above.
- * 
+ *
  * CFG_SDRAM_BASE			- Start address of SDRAM, this _must_ be zero!
  * CFG_SDRAM_SIZE			- Total size of contiguous SDRAM bank(s)
  */
@@ -202,9 +202,9 @@
 #define CFG_SDRAM_SIZE			0x04000000
 
 
-/* 
+/*
  * Flash config - see memory map details above.
- * 
+ *
  * CFG_FLASH_BASE			- Start address of flash memory
  * CFG_FLASH_SIZE			- Total size of contiguous flash mem
  * CFG_FLASH_ERASE_TOUT		- Erase timeout in ms
@@ -223,7 +223,7 @@
 
 /*
  * Monitor config - see memory map details above
- * 
+ *
  * CFG_MONITOR_BASE			- Base address of monitor code
  * CFG_MALLOC_LEN			- Size of malloc pool (128KB)
  */
@@ -234,7 +234,7 @@
 
 /*
  * Command shell settings
- * 
+ *
  * CFG_BARGSIZE			- Boot Argument buffer size
  * CFG_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
  * CFG_CBSIZE			- Console Buffer (input) size
@@ -261,10 +261,10 @@
 
 /*
  * Environment config - see memory map details above
- * 
+ *
  * CFG_ENV_IS_IN_FLASH		- The env variables are stored in flash
  * CFG_ENV_ADDR			- Address of the sector containing env vars
- * CFG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB) 
+ * CFG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB)
  * CFG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
  */
 
@@ -282,7 +282,7 @@
  * Since the main system RAM is initialised very early, we place the INIT_RAM
  * in the main system RAM just above the exception vectors. The contents are
  * copied to top of RAM by the init code.
- * 
+ *
  * CFG_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
  * CFG_INIT_RAM_END			- Size of Init RAM
  * CFG_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
@@ -297,7 +297,7 @@
 
 /*
  * Initial BAT config
- * 
+ *
  * BAT0	- System SDRAM
  * BAT1 - LED's and Serial Port
  * BAT2 - PCI Memory
@@ -327,7 +327,7 @@
 
 /*
  * Cache config
- * 
+ *
  * CFG_CACHELINE_SIZE		- Size of a cache line (CPU specific)
  * CFG_L2					- L2 cache enabled if defined
  * L2_INIT					- L2 cache init flags
@@ -342,7 +342,7 @@
 
 /*
  * Clocks config
- * 
+ *
  * CFG_BUS_HZ				- Bus clock frequency in Hz
  * CFG_BUS_CLK				- As above (?)
  * CFG_HZ					- Decrementer freq in Hz
@@ -355,7 +355,7 @@
 
 /*
  * Serial port config
- * 
+ *
  * CFG_BAUDRATE_TABLE		- List of valid baud rates
  * CFG_NS16550				- Include the NS16550 driver
  * CFG_NS16550_SERIAL		- Include the serial (wrapper) driver
@@ -398,7 +398,7 @@
 
 /*
  * Extra init functions
- * 
+ *
  * CFG_BOARD_ASM_INIT		- Call assembly init code
  */
 
@@ -407,11 +407,11 @@
 
 /*
  * Boot flags
- * 
+ *
  * BOOTFLAG_COLD			- Indicates a power-on boot
  * BOOTFLAG_WARM			- Indicates a software reset
  */
- 
+
 #define BOOTFLAG_COLD			0x01
 #define BOOTFLAG_WARM			0x02
 
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
new file mode 100644
index 0000000..866f7b0
--- /dev/null
+++ b/include/configs/sbc2410x.h
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Modified for the friendly-arm SBC-2410X by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * Configuation settings for the friendly-arm SBC-2410X board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_SKIP_LOWLEVEL_INIT	/* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
+#define CONFIG_SBC2410X		1	/* on a friendly-arm SBC-2410X Board  */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	12000000/* the SBC2410X has 12MHz input clock */
+
+
+#define USE_920T_MMU		1
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x19000300
+#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SBC2410X */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define	CONFIG_RTC_S3C24X0	1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#define CONFIG_COMMANDS \
+			(CONFIG_CMD_DFL	 | \
+			CFG_CMD_CACHE	 | \
+			/*CFG_CMD_NAND	 |*/ \
+			/*CFG_CMD_EEPROM |*/ \
+			/*CFG_CMD_I2C	 |*/ \
+			/*CFG_CMD_USB	 |*/ \
+			CFG_CMD_REGINFO  | \
+			CFG_CMD_DATE	 | \
+			CFG_CMD_PING     | \
+			CFG_CMD_DHCP     | \
+			CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
+#define CONFIG_ETHADDR	        08:00:3e:26:0a:5b
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR		192.168.0.69
+#define CONFIG_SERVERIP		192.168.0.1
+/*#define CONFIG_BOOTFILE	"elinos-lart" */
+#define CONFIG_BOOTCOMMAND	"dhcp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"[ ~ljh@GDLC ]# "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define	CFG_HZ			1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* #define CONFIG_AMD_LV400	1	/\* uncomment this if you have a LV400 flash *\/ */
+
+#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * NAND flash settings
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_WAIT_READY(nand)	NF_WaitRB()
+#define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
+#define NAND_ENABLE_CE(nand)	NF_SetCE(NFCE_LOW)
+#define WRITE_NAND_COMMAND(d, adr)	NF_Cmd(d)
+#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)
+#define WRITE_NAND_ADDRESS(d, adr)	NF_Addr(d)
+#define WRITE_NAND(d, adr)		NF_Write(d)
+#define READ_NAND(adr)			NF_Read()
+/* the following functions are NOP's because S3C24X0 handles this in hardware */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NAND */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2   "> "
+
+#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#else
+#define CONFIG_AUTO_COMPLETE
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
new file mode 100644
index 0000000..9d3609a
--- /dev/null
+++ b/include/configs/spc1920.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
+ *
+ * Configuation settings for the SPC1920 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __H
+#define __CONFIG_H
+
+#define CONFIG_SPC1920			1	/* SPC1920 board */
+#define CONFIG_MPC885			1	/* MPC885 CPU */
+
+#define	CONFIG_8xx_CONS_SMC1		/* Console is on SMC1 */
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_MII
+/* #define MII_DEBUG */
+/* #define CONFIG_FEC_ENET */
+#undef CONFIG_ETHER_ON_FEC1
+#define CONFIG_ETHER_ON_FEC2
+#define FEC_ENET
+/* #define CONFIG_FEC2_PHY_NORXERR */
+/* #define CFG_DISCOVER_PHY */
+/* #define CONFIG_PHY_ADDR		0x1 */
+#define CONFIG_FEC2_PHY		1
+
+#define CONFIG_BAUDRATE		19200
+
+/* use PLD CLK4 instead of brg */
+#undef CFG_SPC1920_SMC1_CLK4
+
+#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+#define CFG_8xx_CPUCLK_MIN		40000000
+#define CFG_8xx_CPUCLK_MAX		133000000
+
+#define CFG_RESET_ADDRESS		0xf8000000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND							\
+    "dhcp;"									\
+    "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "			\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
+    "bootm"
+
+#define CONFIG_BOOTCOMMAND							\
+    "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
+    "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+
+#ifndef CONFIG_COMMANDS
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_ASKENV \
+			 | CFG_CMD_ECHO   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_JFFS2 \
+			 | CFG_CMD_PING \
+			 | CFG_CMD_DHCP \
+			 | CFG_CMD_IMMAP \
+			 | CFG_CMD_MII)
+			/* & ~( CFG_CMD_NET)) */
+
+
+#endif /* !CONFIG_COMMANDS */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"=>"		/* Monitor Command Prompt	*/
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+
+#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size	*/
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR		0x00100000
+
+#define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 2400, 4800, 9600, 19200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+
+#ifdef CONFIG_BZIP2
+#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#else
+#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
+#define	CFG_ALLOC_DPRAM		1	/* use allocation routines	*/
+
+/*
+ * Flash
+ */
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CFG_FLASH_BASE          0xFE000000
+#define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
+#define CFG_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
+#define CFG_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+
+/*-----------------------------------------------------------------------
+ * I2C configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
+#define CFG_I2C_SLAVE		0x7F
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* #define CFG_SCCR	SCCR_TBS */
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Enable Register
+ *-----------------------------------------------------------------------
+ * Set to zero to prevent the processor from entering debug mode
+ */
+#define CFG_DER		 0
+
+
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register.  For CS0, you must write
+ * the base register first, followed by the option register.
+ */
+
+
+/*
+ * Init Memory Controller:
+ */
+
+/* BR0 and OR0 (FLASH) */
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0 */
+
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+
+/*
+ * SDRAM CS1 UPMB
+ */
+#define	CFG_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
+#define SDRAM_MAX_SIZE	0x4000000 /* max 64 MB */
+
+#define CFG_PRELIM_OR1_AM	0xF0000000
+/* #define CFG_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
+#define SDRAM_TIMING	OR_SCY_0_CLK	/* SDRAM-Timing */
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
+#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
+
+/* #define CFG_OR1_FINAL   ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
+/* #define CFG_BR1_FINAL   ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
+
+#define CFG_PTB_PER_CLK	((4096 * 16 * 1000) / (4 * 64))
+#define CFG_PTA_PER_CLK 195
+#define CFG_MBMR_PTB	195
+#define CFG_MPTPR	MPTPR_PTP_DIV16
+#define CFG_MAR		0x88
+
+#define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+			MBMR_AMB_TYPE_0 | \
+			MBMR_G0CLB_A10 | \
+			MBMR_DSB_1_CYCL | \
+			MBMR_RLFB_1X | \
+			MBMR_WLFB_1X | \
+			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+#define CFG_MBMR_9COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+			MBMR_AMB_TYPE_1 | \
+			MBMR_G0CLB_A10 | \
+			MBMR_DSB_1_CYCL | \
+			MBMR_RLFB_1X | \
+			MBMR_WLFB_1X | \
+			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+
+/* PLD CS5 */
+#define CFG_SPC1920_PLD_BASE	0x80000000
+#define CFG_PRELIM_OR5_AM	0xffff8000
+
+#define CFG_OR5_PRELIM		(CFG_PRELIM_OR5_AM | \
+					OR_CSNT_SAM | \
+					OR_ACS_DIV1 | \
+					OR_BI | \
+					OR_SCY_0_CLK | \
+					OR_TRLX)
+
+#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+/* #define CFG_PLD_BASE   0x30000000 */
+/* #define CFG_OR5_PRELIM 0xffff1110 */
+/* #define CFG_BR5_PRELIM 0x30000401 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 9ebb51e..f40dde2 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -452,32 +452,25 @@
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE
 
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
 #define CONFIG_LAST_STAGE_INIT
-#endif
 
 /*
  * SRAM - Do not map below 2 GB in address space, because this area is used
  * for SDRAM autosizing.
  */
-#if defined (CONFIG_CS_AUTOCONF)
 #define CFG_CS2_START		0xE5000000
 #define CFG_CS2_SIZE		0x100000	/* 1 MByte */
 #define CFG_CS2_CFG		0x0004D930
-#endif
 
 /*
  * Grafic controller - Do not map below 2 GB in address space, because this
  * area is used for SDRAM autosizing.
  */
-#if defined (CONFIG_CS_AUTOCONF)
 #define SM501_FB_BASE		0xE0000000
 #define CFG_CS1_START		(SM501_FB_BASE)
 #define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
 #define CFG_CS1_CFG		0x8F48FF70
 #define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
-#endif
 
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 935aca2d..ae97947 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -407,7 +407,7 @@
 #endif
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_ERASE_TOUT	(15*CFG_HZ) /* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
 
 #define	CFG_ENV_IS_IN_FLASH	1
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 952f73b..825bfd1 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -119,9 +119,9 @@
 /*
  * Definitions related to passing arguments to kernel.
  */
-#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel		*/
-#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel	*/
-#undef	CONFIG_INITRD_TAG		 /* do not send initrd params		*/
+#define CONFIG_CMDLINE_TAG	 1	 /* send commandline to Kernel		*/
+#define CONFIG_SETUP_MEMORY_TAGS 1	 /* send memory definition to kernel	*/
+#define	CONFIG_INITRD_TAG	 1	 /* do not send initrd params		*/
 #undef	CONFIG_VFD			 /* do not send framebuffer setup	*/
 
 /*
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
new file mode 100644
index 0000000..0e58e7e
--- /dev/null
+++ b/include/configs/yucca.h
@@ -0,0 +1,526 @@
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * 1 january 2005	Alain Saurel <asaurel@amcc.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+/************************************************************************
+ * yucca.h - configuration for AMCC 440SPe Ref (yucca)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_4xx			1	/* ... PPC4xx family	*/
+#define CONFIG_440			1	/* ... PPC440 family	*/
+#define CONFIG_440SPE			1	/* Specifc SPe support	*/
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
+#undef	CFG_DRAM_TEST				/* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+#define EXTCLK_33_33		33333333
+#define EXTCLK_66_66		66666666
+#define EXTCLK_50		50000000
+#define EXTCLK_83		83333333
+
+#define	CONFIG_IBM_EMAC4_V4		1
+#define	CONFIG_MISC_INIT_F		1	/* Use misc_init_f()	*/
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+#undef  CONFIG_STRESS
+#undef  ENABLE_ECC
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xfff00000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	0xfffb0000	/* start of monitor	*/
+#define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
+#define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PCI_MEMBASE1	0x90000000	/* mapped pci memory	*/
+#define CFG_PCI_MEMBASE2	0xa0000000	/* mapped pci memory	*/
+#define CFG_PCI_MEMBASE3	0xb0000000	/* mapped pci memory	*/
+
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CFG_PCI_TARGBASE	0x80000000	/*PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* #define CFG_PCI_BASE_IO	0xB8000000 */	/* internal PCI I-O	*/
+/* #define CFG_PCI_BASE_REGS	0xBEC00000 */	/* internal PCI regs	*/
+/* #define CFG_PCI_BASE_CYCLE	0xBED00000 */	/* internal PCI regs	*/
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define CFG_FPGA_BASE		0xe2000000	/* epld			*/
+#define CFG_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
+
+/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN		(320 * 1024)	/* Reserve 320 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SERIAL_MULTI	1
+#undef CONFIG_UART1_CONSOLE
+
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK
+/* #define CFG_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS {0x53, 0x52}	/* SPD i2c spd addresses	*/
+#define IIC0_DIMM0_ADDR		0x53
+#define IIC0_DIMM1_ADDR		0x52
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define IIC0_BOOTPROM_ADDR	0x50
+#define IIC0_ALT_BOOTPROM_ADDR	0x54
+
+/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
+
+/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
+/* #define CFG_I2C_EEPROM_ADDR	0x50 */	/* I2C boot EEPROM		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* #endif */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/* #define CFG_NVRAM_SIZE	(0x2000 - 8) */	/* NVRAM size(8k)- RTC regs */
+
+#undef  CFG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
+#define	CFG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
+#undef	CFG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
+#define CONFIG_ENV_OVERWRITE	1
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=yucca\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"				\
+	"bootfile=yucca/uImage\0"					\
+	"kernel_addr=E7F10000\0"					\
+	"ramdisk_addr=E7F20000\0"					\
+	"load=tftp 100000 yuca/u-boot.bin\0"				\
+	"update=protect off 2:4-7;era 2:4-7;"				\
+		"cp.b ${fileaddr} FFFB0000 ${filesize};"		\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#undef CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
+#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	3	/* number of banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* sectors per device		*/
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0		0x5555
+#define CFG_FLASH_ADDR1		0x2aaa
+#define CFG_FLASH_WORD_SIZE	unsigned char
+
+#define CFG_FLASH_2ND_16BIT_DEV	1	/* evb440SPe has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR	0xe7c00000 /* evb440SPe has 8 and 16bit device*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		0xfffa0000
+/* #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
+#define CFG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
+#endif /* CFG_ENV_IS_IN_FLASH */
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT	1	/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+/* #define CFG_PCI_SUBSYS_ID	CFG_PCI_SUBSYS_DEVICEID */
+
+/*
+ *  NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/*Initial Memory map for Linux*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs		*/
+#define CFG_CACHELINE_SIZE	32	/* ...				*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/* FB Divisor selection */
+#define FPGA_FB_DIV_6		6
+#define FPGA_FB_DIV_10		10
+#define FPGA_FB_DIV_12		12
+#define FPGA_FB_DIV_20		20
+
+/* VCO Divisor selection */
+#define	FPGA_VCO_DIV_4		4
+#define	FPGA_VCO_DIV_6		6
+#define	FPGA_VCO_DIV_8		8
+#define	FPGA_VCO_DIV_10		10
+
+/*----------------------------------------------------------------------------+
+| FPGA registers and bit definitions
++----------------------------------------------------------------------------*/
+/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
+/* TLB initialization makes it correspond to logical address 0xE2000000. */
+/* => Done init_chip.s in bootlib */
+#define FPGA_REG_BASE_ADDR	0xE2000000
+#define FPGA_GPIO_BASE_ADDR	0xE2010000
+#define FPGA_INT_BASE_ADDR	0xE2020000
+
+/*----------------------------------------------------------------------------+
+| Display
++----------------------------------------------------------------------------*/
+#define PPC440SPE_DISPLAY	FPGA_REG_BASE_ADDR
+
+#define PPC440SPE_DISPLAY_D8	(FPGA_REG_BASE_ADDR+0x06)
+#define PPC440SPE_DISPLAY_D4	(FPGA_REG_BASE_ADDR+0x04)
+#define PPC440SPE_DISPLAY_D2	(FPGA_REG_BASE_ADDR+0x02)
+#define PPC440SPE_DISPLAY_D1	(FPGA_REG_BASE_ADDR+0x00)
+/*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
+/*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
+
+/*----------------------------------------------------------------------------+
+| ethernet/reset/boot Register 1
++----------------------------------------------------------------------------*/
+#define FPGA_REG10	(FPGA_REG_BASE_ADDR+0x10)
+
+#define FPGA_REG10_10MHZ_ENABLE		0x8000
+#define FPGA_REG10_100MHZ_ENABLE	0x4000
+#define FPGA_REG10_GIGABIT_ENABLE	0x2000
+#define FPGA_REG10_FULL_DUPLEX		0x1000	/* force Full Duplex*/
+#define FPGA_REG10_RESET_ETH		0x0800
+#define FPGA_REG10_AUTO_NEG_DIS		0x0400
+#define FPGA_REG10_INTP_ETH		0x0200
+
+#define FPGA_REG10_RESET_HISR		0x0080
+#define FPGA_REG10_ENABLE_DISPLAY	0x0040
+#define FPGA_REG10_RESET_SDRAM		0x0020
+#define FPGA_REG10_OPER_BOOT		0x0010
+#define FPGA_REG10_SRAM_BOOT		0x0008
+#define FPGA_REG10_SMALL_BOOT		0x0004
+#define FPGA_REG10_FORCE_COLA		0x0002
+#define FPGA_REG10_COLA_MANUAL		0x0001
+
+#define FPGA_REG10_SDRAM_ENABLE		0x0020
+
+#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
+#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
+
+/*----------------------------------------------------------------------------+
+| MUX control
++----------------------------------------------------------------------------*/
+#define FPGA_REG12	(FPGA_REG_BASE_ADDR+0x12)
+
+#define FPGA_REG12_EBC_CTL		0x8000
+#define FPGA_REG12_UART1_CTS_RTS	0x4000
+#define FPGA_REG12_UART0_RX_ENABLE	0x2000
+#define FPGA_REG12_UART1_RX_ENABLE	0x1000
+#define FPGA_REG12_UART2_RX_ENABLE	0x0800
+#define FPGA_REG12_EBC_OUT_ENABLE	0x0400
+#define FPGA_REG12_GPIO0_OUT_ENABLE	0x0200
+#define FPGA_REG12_GPIO1_OUT_ENABLE	0x0100
+#define FPGA_REG12_GPIO_SELECT		0x0010
+#define FPGA_REG12_GPIO_CHREG		0x0008
+#define FPGA_REG12_GPIO_CLK_CHREG	0x0004
+#define FPGA_REG12_GPIO_OETRI		0x0002
+#define FPGA_REG12_EBC_ERROR		0x0001
+
+/*----------------------------------------------------------------------------+
+| PCI Clock control
++----------------------------------------------------------------------------*/
+#define FPGA_REG16	(FPGA_REG_BASE_ADDR+0x16)
+
+#define FPGA_REG16_PCI_CLK_CTL0		0x8000
+#define FPGA_REG16_PCI_CLK_CTL1		0x4000
+#define FPGA_REG16_PCI_CLK_CTL2		0x2000
+#define FPGA_REG16_PCI_CLK_CTL3		0x1000
+#define FPGA_REG16_PCI_CLK_CTL4		0x0800
+#define FPGA_REG16_PCI_CLK_CTL5		0x0400
+#define FPGA_REG16_PCI_CLK_CTL6		0x0200
+#define FPGA_REG16_PCI_CLK_CTL7		0x0100
+#define FPGA_REG16_PCI_CLK_CTL8		0x0080
+#define FPGA_REG16_PCI_CLK_CTL9		0x0040
+#define FPGA_REG16_PCI_EXT_ARB0		0x0020
+#define FPGA_REG16_PCI_MODE_1		0x0010
+#define FPGA_REG16_PCI_TARGET_MODE	0x0008
+#define FPGA_REG16_PCI_INTP_MODE	0x0004
+
+/* FB1 Divisor selection */
+#define FPGA_REG16_FB2_DIV_MASK		0x1000
+#define FPGA_REG16_FB2_DIV_LOW		0x0000
+#define FPGA_REG16_FB2_DIV_HIGH		0x1000
+/* FB2 Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_FB1_DIV_MASK		0x2000
+#define FPGA_REG16_FB1_DIV_LOW		0x0000
+#define FPGA_REG16_FB1_DIV_HIGH		0x2000
+/* PCI0 Clock Selection */
+/* S3 switch on Board */
+#define FPGA_REG16_PCI0_CLK_MASK	0x0c00
+#define FPGA_REG16_PCI0_CLK_33_33	0x0000
+#define FPGA_REG16_PCI0_CLK_66_66	0x0800
+#define FPGA_REG16_PCI0_CLK_100		0x0400
+#define FPGA_REG16_PCI0_CLK_133_33	0x0c00
+/* VCO Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_VCO_DIV_MASK		0xc000
+#define FPGA_REG16_VCO_DIV_4		0x0000
+#define FPGA_REG16_VCO_DIV_8		0x4000
+#define FPGA_REG16_VCO_DIV_6		0x8000
+#define FPGA_REG16_VCO_DIV_10		0xc000
+/* Master Clock Selection */
+/* S3, S4 switches on Board */
+#define FPGA_REG16_MASTER_CLK_MASK	0x01c0
+#define FPGA_REG16_MASTER_CLK_EXT	0x0000
+#define FPGA_REG16_MASTER_CLK_66_66	0x0040
+#define FPGA_REG16_MASTER_CLK_50	0x0080
+#define FPGA_REG16_MASTER_CLK_33_33	0x00c0
+#define FPGA_REG16_MASTER_CLK_25	0x0100
+
+/*----------------------------------------------------------------------------+
+| PCI Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG18	(FPGA_REG_BASE_ADDR+0x18)
+
+#define FPGA_REG18_PCI_PRSNT1		0x8000
+#define FPGA_REG18_PCI_PRSNT2		0x4000
+#define FPGA_REG18_PCI_INTA		0x2000
+#define FPGA_REG18_PCI_SLOT0_INTP	0x1000
+#define FPGA_REG18_PCI_SLOT1_INTP	0x0800
+#define FPGA_REG18_PCI_SLOT2_INTP	0x0400
+#define FPGA_REG18_PCI_SLOT3_INTP	0x0200
+#define FPGA_REG18_PCI_PCI0_VC		0x0100
+#define FPGA_REG18_PCI_PCI0_VTH1	0x0080
+#define FPGA_REG18_PCI_PCI0_VTH2	0x0040
+#define FPGA_REG18_PCI_PCI0_VTH3	0x0020
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1A	(FPGA_REG_BASE_ADDR+0x1A)
+
+#define FPGA_REG1A_PE0_GLED		0x8000
+#define FPGA_REG1A_PE1_GLED		0x4000
+#define FPGA_REG1A_PE2_GLED		0x2000
+#define FPGA_REG1A_PE0_YLED		0x1000
+#define FPGA_REG1A_PE1_YLED		0x0800
+#define FPGA_REG1A_PE2_YLED		0x0400
+#define FPGA_REG1A_PE0_PWRON		0x0200
+#define FPGA_REG1A_PE1_PWRON		0x0100
+#define FPGA_REG1A_PE2_PWRON		0x0080
+#define FPGA_REG1A_PE0_REFCLK_ENABLE	0x0040
+#define FPGA_REG1A_PE1_REFCLK_ENABLE	0x0020
+#define FPGA_REG1A_PE2_REFCLK_ENABLE	0x0010
+#define FPGA_REG1A_PE_SPREAD0		0x0008
+#define FPGA_REG1A_PE_SPREAD1		0x0004
+#define FPGA_REG1A_PE_SELSOURCE_0	0x0002
+#define FPGA_REG1A_PE_SELSOURCE_1	0x0001
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1C	(FPGA_REG_BASE_ADDR+0x1C)
+
+#define FPGA_REG1C_PE0_ROOTPOINT	0x8000
+#define FPGA_REG1C_PE1_ENDPOINT		0x4000
+#define FPGA_REG1C_PE2_ENDPOINT		0x2000
+#define FPGA_REG1C_PE0_PRSNT		0x1000
+#define FPGA_REG1C_PE1_PRSNT		0x0800
+#define FPGA_REG1C_PE2_PRSNT		0x0400
+#define FPGA_REG1C_PE0_WAKE		0x0080
+#define FPGA_REG1C_PE1_WAKE		0x0040
+#define FPGA_REG1C_PE2_WAKE		0x0020
+#define FPGA_REG1C_PE0_PERST		0x0010
+#define FPGA_REG1C_PE1_PERST		0x0080
+#define FPGA_REG1C_PE2_PERST		0x0040
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+#define PERIOD_133_33MHZ	7500	/* 7,5ns */
+#define PERIOD_100_00MHZ	10000	/* 10ns */
+#define PERIOD_83_33MHZ		12000	/* 12ns */
+#define PERIOD_75_00MHZ		13333	/* 13,333ns */
+#define PERIOD_66_66MHZ		15000	/* 15ns */
+#define PERIOD_50_00MHZ		20000	/* 20ns */
+#define PERIOD_33_33MHZ		30000	/* 30ns */
+#define PERIOD_25_00MHZ		40000	/* 40ns */
+
+/*---------------------------------------------------------------------------*/
+
+#endif	/* __CONFIG_H */