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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-12-02 14:19:33 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
| commit | 52b565f5ad23b682489055b187767d8bf1c2e444 (patch) | |
| tree | f7e62f88a22deb0dcabe2b6c3ac85276d39cd907 /include/configs | |
| parent | 30837e5b21d5a742983581ab9ee3fac085311d19 (diff) | |
| download | u-boot-imx-52b565f5ad23b682489055b187767d8bf1c2e444.zip u-boot-imx-52b565f5ad23b682489055b187767d8bf1c2e444.tar.gz u-boot-imx-52b565f5ad23b682489055b187767d8bf1c2e444.tar.bz2 | |
85xx: separate PIXIS virtual from physical address
Added a PIXIS_BASE_PHYS for use as the physical address and maintain
PIXIS_BASE as the virtual address of the PIXIS fpga registers.
This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8536DS.h | 3 | ||||
| -rw-r--r-- | include/configs/MPC8572DS.h | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 505c48b..3ea1b48 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -194,8 +194,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS PIXIS_BASE -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index f84cc7e..6e42b28 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -197,8 +197,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS PIXIS_BASE -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |