* Patch by Martin Krause, 17 Jul 2003:

  add delay to get I2C working with "imm" command and s3c24x0_i2c.c

* Patch by Richard Woodruff, 17 July 03:
  - Fixed bug in OMAP1510 baud rate divisor settings.

* Patch by Nye Liu, 16 July 2003:
  MPC860FADS fixes:
  - add MPC86xADS support (uses MPC86xADS.h)
  - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
    o PLPRCR changes
    o BRG changes (EXTAL/XTAL restricted to 10MHz)
    o don't trust gclk() software measurement by default, depend on
      CONFIG_8xx_GCLK_FREQ
  - add DRAM SIMM not installed detection
  - use more "correct" SDRAM initialization sequence
  - allow different SDRAM sizes (8xxADS has 8M)
  - default DER is 0
  - remove unused MAMR defines from FADS860T.h (all done in fads.c)
  - rename MAMR/MBMR defines to be more consistent. Should eventually
    be merged into MxMR to better reflect the PowerQUICC datasheet.

* Patch by Yuli Barcohen, 16 Jul 2003:
  support new Motorola PQ2FADS-ZU evaluation board which replaced
  MPC8260ADS and MPC8266ADS

13 files changed, 577 insertions, 106 deletions

diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h
index 1b73692..0045303 100644
--- a/include/configs/ADS860.h
+++ b/include/configs/ADS860.h
@@ -19,6 +19,7 @@
 #include <mpc8xx_irq.h>
 
 #define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
 #define CONFIG_ADS		1
 
 #define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1	    */
@@ -31,10 +32,12 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
 #define CFG_I2C_SLAVE		0x7F
 
-#define MPC8XX_XIN		32768	/* 32.768 kHz input frequency	*/
-#define MPC8XX_FACT		0x5F6	/* Multiply by 1526 */
+#define CFG_8XX_XIN		32768	/* 32.768 kHz input frequency	*/
+#define CFG_8XX_FACT		0x5F6	/* Multiply by 1526 */
 					/* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */
 
+#define CONFIG_8xx_GCLK_FREQ   ((CFG_8XX_XIN) * (CFG_8XX_FACT))
+
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #if 0
@@ -136,7 +139,7 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
@@ -198,7 +201,7 @@
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR  (((MPC8XX_FACT-1) << 20) |	\
+#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index acb2eed..3b201a7 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -23,6 +23,7 @@
 #define CFG_PCMCIA_MEM_ADDR	0xe0000000
 #define CFG_PCMCIA_MEM_SIZE	0x10000
 #define CFG_IMMR		0xFF000000
+#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
 #define	CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0x02800000
 #define BCSR_ADDR		((uint) 0xff010000)
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
index a104176..3d04ef0 100644
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@@ -116,6 +116,7 @@
  * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
  */
 #define	CFG_SDRAM_BASE		0x00000000
+#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
 #define CFG_FLASH_BASE		0x02800000
 #define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 #if 0
diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h
index 2c94389..fd56010 100644
--- a/include/configs/FADS860T.h
+++ b/include/configs/FADS860T.h
@@ -32,25 +32,33 @@
  */
 #include <mpc8xx_irq.h>
 
-#define CONFIG_MPC860		1
-#define CONFIG_MPC860T		1
-#define CONFIG_FADS		1
+/* board type */
+#define CONFIG_FADS		1       /* old/new FADS + new ADS */
+
+/* processor type */
+#define CONFIG_MPC860T		1       /* 860T */
 
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
+#define CONFIG_BAUDRATE		38400
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 
-#if 0
-#define MPC8XX_FACT		10		/* Multiply by 10	*/
-#define MPC8XX_XIN		5000000			/* 5 MHz in	*/
-#else
-#define MPC8XX_FACT		12		/* Multiply by 12	*/
-#define MPC8XX_XIN		4000000			/* 4 MHz in	*/
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+#if 0 /* old FADS */
+# define CFG_8XX_FACT		12		/* Multiply by 12 */
+# define CFG_8XX_XIN		4000000		/* 4 MHz in	*/
+#else /* new FADS */
+# define CFG_8XX_FACT		10		/* Multiply by 10 */
+# define CFG_8XX_XIN		5000000		/* 5 MHz in	*/
 #endif
 
+#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
+
+/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
+/* in general, we always know this for FADS+new ADS anyway */
+#define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ
+
+/* most vanilla kernels do not like this, set to 0 if in doubt */
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #if 1
@@ -59,8 +67,12 @@
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif
 
-#define CONFIG_BOOTCOMMAND	"bootm 2800100"	/* autoboot command */
-#define CONFIG_BOOTARGS		""
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND			    \
+    "bootp; "				    \
+    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	    \
+    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
+    "bootm"
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -77,10 +89,10 @@
 /* choose SCC1 ethernet (10BASET on motherboard)
  * or FEC ethernet (10/100 on daughterboard)
  */
-#if 1
+#if 0
 #define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
 #undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */
-#else
+#else   /* all 86x cores have FECs, if in doubt, use it */
 #undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
 #define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
 #define CFG_DISCOVER_PHY
@@ -107,7 +119,11 @@
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#if (CFG_SDRAM_SIZE)
+#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
+#else
 #define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#endif
 
 #define CFG_LOAD_ADDR	 	0x00100000
 
@@ -120,7 +136,7 @@
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-/*-----------------------------------------------------------------------
+/*----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
 #define CFG_IMMR			0xFF000000
@@ -141,6 +157,11 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define	CFG_SDRAM_BASE		0x00000000
+#ifdef CONFIG_FADS
+# define	CFG_SDRAM_SIZE	0x00400000      /* 4 meg */
+#else   /* !CONFIG_FADS */ /* old ADS */
+# define	CFG_SDRAM_SIZE	0x00000000      /* NO SDRAM */
+#endif
 
 #define CFG_FLASH_BASE		0x02800000
 
@@ -218,7 +239,7 @@
  *-----------------------------------------------------------------------
  * set the PLL, the low-power modes and the reset control (15-29)
  */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CFG_PLPRCR	(((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -235,7 +256,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER		0
+#define CFG_DER		 0
 
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@@ -280,36 +301,6 @@
 #define CFG_OR1_PRELIM	0xffff8110		/* 64Kbyte address space */
 #define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
 
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA		97	/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#define CFG_MAMR		0x13a01114
 /*
  * Internal Definitions
  *
@@ -425,7 +416,7 @@
 #endif /* CONFIG_MPC850 */
 
 #define CONFIG_DRAM_50MHZ		1
-#define CONFIG_SDRAM_50MHZ
+#define CONFIG_SDRAM_50MHZ              1
 
 #ifdef CONFIG_MPC860T
 
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index 7b76226..6dedbd7 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -354,7 +354,7 @@
  */
 
 #define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLB_A11 |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_8X)
 
 
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index 77746e8..a0cb1dd 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -424,7 +424,7 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB	204
+#define CFG_MBMR_PTB	204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
@@ -448,19 +448,19 @@
 
 #if defined (CONFIG_IVML24_16M)
  /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
- 			 MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |	\
- 			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+ 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+ 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVML24_32M)
 /* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVML24_64M)
 /* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #endif
 
 /*
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 19063fa..46b4d53 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -408,7 +408,7 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB	204
+#define CFG_MBMR_PTB	204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
@@ -431,19 +431,19 @@
 
 #if defined (CONFIG_IVMS8_16M)
  /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
- 			 MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |	\
- 			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+ 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+ 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_32M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_64M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 
 #endif
 
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 401591d..5960b30 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -9,7 +9,8 @@
  *
  * (C) Copyright 2003 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII.
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
+ * Ported to PQ2FADS-ZU board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -41,6 +42,15 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_MPC8260ADS	1	/* ...on motorola ads board */
 
+/* ADS flavours */
+#define CFG_8260ADS		1	/* MPC8260ADS */
+#define CFG_8266ADS		2	/* MPC8266ADS */
+#define CFG_PQ2FADS		3	/* PQ2FADS-ZU */
+
+#ifndef CONFIG_ADSTYPE
+#define CONFIG_ADSTYPE		CFG_8260ADS
+#endif /* CONFIG_ADSTYPE */
+
 #define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
 
 /* allow serial and ethaddr to be overwritten */
@@ -116,7 +126,9 @@
 
 #endif /* CONFIG_ETHER_ON_FCC */
 
-/* other options */
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#undef CONFIG_SPD_EEPROM	/* On PQ2FADS-ZU, SDRAM is soldered  */
+#else
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
@@ -124,18 +136,23 @@
 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 #define CONFIG_SPD_ADDR         0x50
 #endif
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 
 #ifndef CONFIG_SDRAM_PBI
 #define CONFIG_SDRAM_PBI        1 /* By default, use page-based interleaving */
 #endif
 
 #ifndef CONFIG_8260_CLKIN
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+#else
 #define CONFIG_8260_CLKIN	66666666	/* in Hz */
 #endif
+#endif
+
 #define CONFIG_BAUDRATE		115200
 
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
-				 CFG_CMD_BEDBUG | \
+#define CFG_EXCLUDE		 CFG_CMD_BEDBUG | \
 				 CFG_CMD_BMP	| \
 				 CFG_CMD_BSP	| \
 				 CFG_CMD_DATE	| \
@@ -143,11 +160,11 @@
 				 CFG_CMD_DTT	| \
 				 CFG_CMD_EEPROM | \
 				 CFG_CMD_ELF    | \
+				 CFG_CMD_FAT    | \
 				 CFG_CMD_FDC	| \
 				 CFG_CMD_FDOS	| \
 				 CFG_CMD_HWFLOW	| \
 				 CFG_CMD_IDE	| \
-				 CFG_CMD_JFFS2	| \
 				 CFG_CMD_KGDB	| \
 				 CFG_CMD_MMC	| \
 				 CFG_CMD_NAND	| \
@@ -155,8 +172,18 @@
 				 CFG_CMD_PCMCIA | \
 				 CFG_CMD_SCSI	| \
 				 CFG_CMD_SPI	| \
-				 CFG_CMD_VFD	| \
-				 CFG_CMD_USB	) )
+				 CFG_CMD_USB	| \
+				 CFG_CMD_VFD
+
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+				 CFG_CMD_SDRAM	| \
+				 CFG_CMD_I2C	| \
+				 CFG_EXCLUDE	) )
+#else
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+				 CFG_EXCLUDE	) )
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -200,7 +227,6 @@
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CFG_FLASH_BASE		0xff800000
-#define FLASH_BASE		0xff800000
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
 #define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
 #define CFG_FLASH_SIZE		8
@@ -219,14 +245,16 @@
 #define CFG_DEFAULT_IMMR	0x0F010000
 
 #define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0x04500000
+#define CFG_BCSR		0xF4500000
 #define CFG_SDRAM_BASE		0x00000000
-#define CFG_LSDRAM_BASE		0x04000000
+#define CFG_LSDRAM_BASE		0xD0000000
 
 #define RS232EN_1		0x02000002
 #define RS232EN_2		0x01000001
-#define FETHIEN			0x08000008
-#define FETH_RST		0x04000004
+#define FETHIEN1		0x08000008
+#define FETH1_RST		0x04000004
+#define FETHIEN2		0x01000000
+#define FETH2_RST		0x08000000
 
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
 #define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
@@ -288,19 +316,30 @@
 #define CFG_SYPCR		0xFFFFFFC3
 #define CFG_BCR			0x100C0000
 #define CFG_SIUMCR		0x0A200000
-#define CFG_SCCR		0x00000000
-#define CFG_BR0_PRELIM		0xFF801801
-#define CFG_OR0_PRELIM		0xFF800836
-#define CFG_BR1_PRELIM		0x04501801
+#define CFG_SCCR		SCCR_DFBRG01
+#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
+#define CFG_OR0_PRELIM		0xFF800876
+#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
 #define CFG_OR1_PRELIM		0xFFFF8010
 
-#define CFG_RMR			0
+#define CFG_RMR			RMR_CSRE
 #define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 #define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
 #define CFG_RCCR		0
+
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#define CFG_PSDMR		0x824B36A3
+#define CFG_PSRT		0x13
+#define CFG_LSDMR		0x828737A3
+#define CFG_LSRT		0x13
+#define CFG_MPTPR		0x2800
+#else
 #define CFG_PSDMR		0x016EB452
-#define CFG_MPTPR		0x00001900
-#define CFG_PSRT		0x00000021
+#define CFG_PSRT		0x21
+#define CFG_LSDMR		0x0086A522
+#define CFG_LSRT		0x21
+#define CFG_MPTPR		0x1900
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 
 #define CFG_RESET_ADDRESS	0x04400000
 
diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
new file mode 100644
index 0000000..fc79c52
--- /dev/null
+++ b/include/configs/MPC86xADS.h
@@ -0,0 +1,438 @@
+/*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola MPC8xxADS board.  Copied from the FADS config.
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * 1999-nov-26: The FADS is using the following physical memorymap:
+ *
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
+ * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+/* board type */
+#define CONFIG_MPC86xADS        1       /* new ADS */
+#define CONFIG_FADS		1       /* We are FADS compatible (more or less) */
+
+/* new 86xADS only - pick one of these */
+#define CONFIG_MPC866T 		1
+#undef CONFIG_MPC866P
+#undef CONFIG_MPC859T
+#undef CONFIG_MPC859DSL
+#undef CONFIG_MPC852T
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#ifdef CONFIG_MPC86xADS
+# define CFG_8XX_FACT		5		/* Multiply by 5	*/
+# define CFG_8XX_XIN		10000000	/* 10 MHz in	*/
+#else /* ! CONFIG_MPC86xADS */
+# if 0 /* old FADS */
+#  define CFG_8XX_FACT		12		/* Multiply by 12 */
+#  define CFG_8XX_XIN		4000000		/* 4 MHz in	*/
+# else /* new FADS */
+#  define CFG_8XX_FACT		10		/* Multiply by 10 */
+#  define CFG_8XX_XIN		5000000		/* 5 MHz in	*/
+# endif
+#endif /* ! CONFIG_MPC86xADS */
+
+#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
+
+/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
+/* in general, we always know this for FADS+new ADS anyway */
+#define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ
+
+/* most vanilla kernels do not like this, set to 0 if in doubt */
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND			    \
+    "bootp; "				    \
+    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	    \
+    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
+    "bootm"
+
+/* #include "local.h" */
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/* ATA / IDE and partition support */
+#define CONFIG_MAC_PARTITION    1
+#define CONFIG_DOS_PARTITION    1
+#define CONFIG_ISO_PARTITION	1
+#undef	CONFIG_ATAPI
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+/* choose SCC1 ethernet (10BASET on motherboard)
+ * or FEC ethernet (10/100 on daughterboard)
+ */
+#if 0
+#define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
+#undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */
+#else   /* all 86x cores have FECs, if in doubt, use it */
+#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define CFG_DISCOVER_PHY
+#endif
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#if (CFG_SDRAM_SIZE)
+#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
+#else
+#define CFG_MEMTEST_END		0x0400000     	/* 1 ... 4 MB in DRAM	*/
+#endif
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		        1000		/* decr freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#ifdef CONFIG_FADS
+# ifdef CONFIG_MPC86xADS /* new ADS */
+#  define	CFG_SDRAM_SIZE	0x00800000      /* 8 meg */
+# else                   /* old/new FADS */
+#  define	CFG_SDRAM_SIZE	0x00400000      /* 4 meg */
+# endif
+#else   /* !CONFIG_FADS */ /* old ADS */
+# define	CFG_SDRAM_SIZE	0x00000000      /* NO SDRAM */
+#endif
+
+#define CFG_FLASH_BASE		0x02800000
+
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+
+#define	CFG_MONITOR_LEN		(272 << 10)	/* Reserve 272 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00040000
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR	((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		 0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define BCSR_ADDR		((uint) 0xFF010000)
+#define BCSR_SIZE		((uint)(64 * 1024))
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+
+#ifdef USE_REAL_FLASH_VALUES
+/*
+ * The "default" behaviour with 1Mbyte initial doesn't work for us!
+ */
+#define CFG_OR0_PRELIM	0x0FFC00D34 /* Real values for the board */
+#define CFG_BR0_PRELIM	0x02800001  /* Real values for the board */
+#else
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
+#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
+#endif
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xffff8110		/* 64Kbyte address space */
+#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/* values according to the manual */
+
+#define PCMCIA_MEM_ADDR		((uint)0xff020000)
+#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
+
+#define	BCSR0			((uint) (BCSR_ADDR + 00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      (23)
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#define BCSR4_FETHRST            ((uint)0x00200000)
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ              1
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    2
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+/*#define CFG_PCMCIA_MEM_SIZE     ( 64 << 20) */
+#define CFG_PCMCIA_MEM_ADDR	(0x50000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0x54000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0x58000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0x5C000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+/* we have 8 windows, we take everything up to 60000000 */
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0000
+/*#define CFG_ATA_ALT_OFFSET	0x0100 */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index 959ee1a..9746b64 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -331,8 +331,7 @@
  *
  */
 /* #define	CFG_DER	0x2002000F */
-/* #define CFG_DER	0 */
-#define	CFG_DER	0x0082000F
+#define CFG_DER	0
 
 /*
  * Init Memory Controller:
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index 51f2c25..ae4dcc2 100644
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -381,7 +381,7 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB	204
+#define CFG_MBMR_PTB	204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
@@ -396,9 +396,9 @@
  */
 
 /* 8 column SDRAM */
-#define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 
 /*
  * Internal Definitions
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
index 42877a7..31f1e56 100644
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@@ -518,11 +518,11 @@
 #define CFG_MAMR_PTA	0x30	/* = 48 */
 
 #define CFG_MAMR	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
-			  MAMR_AMB_TYPE_1	| \
-			  MAMR_G0CLB_A10	| \
-			  MAMR_RLFB_1X		| \
-			  MAMR_WLFB_1X		| \
-			  MAMR_TLFB_8X		)
+			  MAMR_AMA_TYPE_1	| \
+			  MAMR_G0CLA_A10	| \
+			  MAMR_RLFA_1X		| \
+			  MAMR_WLFA_1X		| \
+			  MAMR_TLFA_8X		)
 
 /*
  * Internal Definitions
diff --git a/include/configs/v37.h b/include/configs/v37.h
index 6696985..45bc353 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -296,8 +296,7 @@
  *-----------------------------------------------------------------------
  *
  */
-#define	CFG_DER	0x0082000F
-/*#define CFG_DER	0*/
+#define CFG_DER	0
 
 /*
  * Init Memory Controller: