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| author | Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com> | 2014-01-09 01:48:08 +0530 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-01-10 15:18:32 +0100 |
| commit | 625d7637513a41045e47b7ccd36185f0e4c1df26 (patch) | |
| tree | e8fc4beffa6cfe0cb3790374ca53e0b537429311 /include/configs/zynq.h | |
| parent | 8cfac504427306f3050ce81f9f7bea09fbe9d76a (diff) | |
| download | u-boot-imx-625d7637513a41045e47b7ccd36185f0e4c1df26.zip u-boot-imx-625d7637513a41045e47b7ccd36185f0e4c1df26.tar.gz u-boot-imx-625d7637513a41045e47b7ccd36185f0e4c1df26.tar.bz2 | |
zynq: Add UART0, UART1 configs support
Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Diffstat (limited to 'include/configs/zynq.h')
| -rw-r--r-- | include/configs/zynq.h | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 6e545e5..f104558 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -33,10 +33,22 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Zynq Serial driver */ -#define CONFIG_ZYNQ_SERIAL -#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#define CONFIG_ZYNQ_SERIAL_UART1 +#ifdef CONFIG_ZYNQ_SERIAL_UART0 +# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#endif + +#ifdef CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 +#endif + +#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) +# define CONFIG_ZYNQ_SERIAL +#endif /* DCC driver */ #if defined(CONFIG_ZYNQ_DCC) |