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| author | Stefan Roese <sr@denx.de> | 2007-03-08 10:10:18 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-08 10:10:18 +0100 |
| commit | 2f5df47351910a2936c7741cf111855829200943 (patch) | |
| tree | 04aa09cb97b46e2b5db4c499037e0f8104b723c1 /include/configs/yucca.h | |
| parent | 2721a68a9ea91f1e494649ce68b2577261f578e2 (diff) | |
| download | u-boot-imx-2f5df47351910a2936c7741cf111855829200943.zip u-boot-imx-2f5df47351910a2936c7741cf111855829200943.tar.gz u-boot-imx-2f5df47351910a2936c7741cf111855829200943.tar.bz2 | |
[PATCH] Update AMCC Yucca 440SPe eval board support
The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/yucca.h')
| -rw-r--r-- | include/configs/yucca.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 6417ed8..eb4859c 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -45,11 +45,11 @@ #define EXTCLK_50 50000000 #define EXTCLK_83 83333333 -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS -#undef ENABLE_ECC + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -118,10 +118,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */ -#define IIC0_DIMM0_ADDR 0x53 -#define IIC0_DIMM1_ADDR 0x52 +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ +#undef CONFIG_DDR_ECC /* no ECC support for now */ /*----------------------------------------------------------------------- * I2C @@ -211,6 +210,7 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ #undef CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |