Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

1 files changed, 78 insertions, 78 deletions

diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index bcd16ec..16af845 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -41,8 +41,8 @@
  * used for the RAM copy of the uboot code
  *
  */
-#define CFG_MALLOC_LEN		(256*1024)
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -58,18 +58,18 @@
  * I2C bus
  */
 #define CONFIG_HARD_I2C			1
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xfe
+#define CONFIG_SYS_I2C_SPEED			50000
+#define CONFIG_SYS_I2C_SLAVE			0xfe
 
 #define CONFIG_RTC_PCF8563		1
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
-#define CFG_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
-#define CFG_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
-#define CFG_EEPROM_SIZE			2048	/* size in bytes		*/
-#undef	CFG_I2C_INIT_BOARD			/* board has no own init	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
+#define CONFIG_SYS_EEPROM_SIZE			2048	/* size in bytes		*/
+#undef	CONFIG_SYS_I2C_INIT_BOARD			/* board has no own init	*/
 
 /*
  * select serial console configuration
@@ -107,26 +107,26 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
 
-#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define CFG_LOAD_ADDR		0xa3000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xa3000000	/* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
+#define CONFIG_SYS_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
 
 						/* valid baudrates */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Definitions related to passing arguments to kernel.
@@ -166,29 +166,29 @@
 #define PHYS_FLASH_BANK_SIZE	0x01000000 /* 16 MB Banks	*/
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 
-#define CFG_DRAM_BASE		0xa0000000
-#define CFG_DRAM_SIZE		0x04000000
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
 
-#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /*
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase	*/
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write	*/
-#define CFG_FLASH_LOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Set Lock Bit */
-#define CFG_FLASH_UNLOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Clear Lock Bits */
-#define CFG_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
-#define CFG_ENV_SIZE		0x4000
-#define CFG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
-#define CFG_MONITOR_LEN		0x20000				/* 128 KiB */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Set Lock Bit */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Clear Lock Bits */
+#define CONFIG_SYS_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
+#define CONFIG_SYS_MONITOR_LEN		0x20000				/* 128 KiB */
 
 /******************************************************************************
  *
@@ -287,38 +287,38 @@
  *
  */
 /* Pin direction control */
-#define CFG_GPDR0_VAL	    0xd3808000
-#define CFG_GPDR1_VAL	    0xfcffab83
-#define CFG_GPDR2_VAL	    0x0001ffff
+#define CONFIG_SYS_GPDR0_VAL	    0xd3808000
+#define CONFIG_SYS_GPDR1_VAL	    0xfcffab83
+#define CONFIG_SYS_GPDR2_VAL	    0x0001ffff
 /* Set and Clear registers */
-#define CFG_GPSR0_VAL	    0x00008000
-#define CFG_GPSR1_VAL	    0x00ff0002
-#define CFG_GPSR2_VAL	    0x0001c000
-#define CFG_GPCR0_VAL	    0x00000000
-#define CFG_GPCR1_VAL	    0x00000000
-#define CFG_GPCR2_VAL	    0x00000000
+#define CONFIG_SYS_GPSR0_VAL	    0x00008000
+#define CONFIG_SYS_GPSR1_VAL	    0x00ff0002
+#define CONFIG_SYS_GPSR2_VAL	    0x0001c000
+#define CONFIG_SYS_GPCR0_VAL	    0x00000000
+#define CONFIG_SYS_GPCR1_VAL	    0x00000000
+#define CONFIG_SYS_GPCR2_VAL	    0x00000000
 /* Edge detect registers (these are set by the kernel) */
-#define CFG_GRER0_VAL	    0x00002180
-#define CFG_GRER1_VAL	    0x00000000
-#define CFG_GRER2_VAL	    0x00000000
-#define CFG_GFER0_VAL	    0x000043e0
-#define CFG_GFER1_VAL	    0x00000000
-#define CFG_GFER2_VAL	    0x00000000
+#define CONFIG_SYS_GRER0_VAL	    0x00002180
+#define CONFIG_SYS_GRER1_VAL	    0x00000000
+#define CONFIG_SYS_GRER2_VAL	    0x00000000
+#define CONFIG_SYS_GFER0_VAL	    0x000043e0
+#define CONFIG_SYS_GFER1_VAL	    0x00000000
+#define CONFIG_SYS_GFER2_VAL	    0x00000000
 /* Alternate function registers */
-#define CFG_GAFR0_L_VAL	    0x80000004
-#define CFG_GAFR0_U_VAL	    0x595a8010
-#define CFG_GAFR1_L_VAL	    0x699a9559
-#define CFG_GAFR1_U_VAL	    0xaaa5aaaa
-#define CFG_GAFR2_L_VAL	    0xaaaaaaaa
-#define CFG_GAFR2_U_VAL	    0x00000002
+#define CONFIG_SYS_GAFR0_L_VAL	    0x80000004
+#define CONFIG_SYS_GAFR0_U_VAL	    0x595a8010
+#define CONFIG_SYS_GAFR1_L_VAL	    0x699a9559
+#define CONFIG_SYS_GAFR1_U_VAL	    0xaaa5aaaa
+#define CONFIG_SYS_GAFR2_L_VAL	    0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL	    0x00000002
 
 /*
  * Clocks, power control and interrupts
  */
-#define CFG_PSSR_VAL	    0x00000030
-#define CFG_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
-#define CFG_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
-#define CFG_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+#define CONFIG_SYS_PSSR_VAL	    0x00000030
+#define CONFIG_SYS_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
+#define CONFIG_SYS_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
+#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
 
 /* FIXME
  *
@@ -331,23 +331,23 @@
  * Memory settings
  *
  */
-#define CFG_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
-#define CFG_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
-#define CFG_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
-#define CFG_MDCNFG_VAL	    0x000009c9
-#define CFG_MDMRS_VAL	    0x00220022
-#define CFG_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
+#define CONFIG_SYS_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
+#define CONFIG_SYS_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
+#define CONFIG_SYS_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
+#define CONFIG_SYS_MDCNFG_VAL	    0x000009c9
+#define CONFIG_SYS_MDMRS_VAL	    0x00220022
+#define CONFIG_SYS_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
 
 /*
  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
  */
-#define CFG_MECR_VAL	      0x00000000
-#define CFG_MCMEM0_VAL	      0x00010504
-#define CFG_MCMEM1_VAL	      0x00010504
-#define CFG_MCATT0_VAL	      0x00010504
-#define CFG_MCATT1_VAL	      0x00010504
-#define CFG_MCIO0_VAL	      0x00004715
-#define CFG_MCIO1_VAL	      0x00004715
+#define CONFIG_SYS_MECR_VAL	      0x00000000
+#define CONFIG_SYS_MCMEM0_VAL	      0x00010504
+#define CONFIG_SYS_MCMEM1_VAL	      0x00010504
+#define CONFIG_SYS_MCATT0_VAL	      0x00010504
+#define CONFIG_SYS_MCATT1_VAL	      0x00010504
+#define CONFIG_SYS_MCIO0_VAL	      0x00004715
+#define CONFIG_SYS_MCIO1_VAL	      0x00004715
 
 /* Board specific defines */