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| author | Wolfgang Denk <wd@pollux.denx.de> | 2005-08-04 19:45:01 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2005-08-04 19:45:01 +0200 |
| commit | 452f67407b20ab6a37c037d0975ea717d2f254e9 (patch) | |
| tree | 5799a92bde97ce9fbfccca76c24d36e595e21b91 /include/configs/xaeniax.h | |
| parent | 3e0bc4473add883fd68a49b7dab971191b943415 (diff) | |
| download | u-boot-imx-452f67407b20ab6a37c037d0975ea717d2f254e9.zip u-boot-imx-452f67407b20ab6a37c037d0975ea717d2f254e9.tar.gz u-boot-imx-452f67407b20ab6a37c037d0975ea717d2f254e9.tar.bz2 | |
Adjust configuration of XENIAX board
(chip select and GPIO required for USB operation)
Diffstat (limited to 'include/configs/xaeniax.h')
| -rw-r--r-- | include/configs/xaeniax.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 386ce05..1039762 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -236,7 +236,7 @@ * GP30 == SDATA_OUT is 0 * GP81 == NSSPCLK is 0 */ -#define CFG_GPCR0_VAL 0x40C31868 +#define CFG_GPCR0_VAL 0x40C31848 #define CFG_GPCR1_VAL 0x00000000 #define CFG_GPCR2_VAL 0x00020000 @@ -455,10 +455,10 @@ * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns - * [03] 0 - 32 Bit bus width + * [03] 1 - 16 Bit bus width * [02:00] 100 - variable latency I/O */ -#define CFG_MSC1_VAL 0x1224A264 +#define CFG_MSC1_VAL 0x1224A26C /* This is the configuration for nCS4/5 -> LAN * configuration for nCS5: |