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authorAnton Vorontsov <avorontsov@ru.mvista.com>2008-09-10 18:12:37 +0400
committerKim Phillips <kim.phillips@freescale.com>2008-10-21 18:31:07 -0500
commit5c2ff323a94e27e481f70c44838d43fcd844dd46 (patch)
tree6d1c08d49a2a3c73c6f6b407e13564c6c9fc1c17 /include/configs/xaeniax.h
parentdef0819e920b05b34b56d8b42e1e43d9b89a52d6 (diff)
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mpc83xx: mpc8360emds: rework LBC SDRAM setup
Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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