Merge branch 'master' of /home/stefan/git/u-boot/u-boot

1 files changed, 54 insertions, 54 deletions

diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index d3d079a..630c0d3 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -76,30 +76,30 @@
 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 
 /*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
-#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD	    691200
 
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -115,20 +115,20 @@
 					/* resource configuration	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  */
-#define CFG_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
 
 /*
  * Define here the location of the environment variables (FLASH or NVRAM).
@@ -144,24 +144,24 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0		*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0		*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1		*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_FLASH_ADDR0		0x5555
-#define CFG_FLASH_ADDR1		0x2aaa
-#define CFG_FLASH_WORD_SIZE	unsigned char
+#define CONFIG_SYS_FLASH_ADDR0		0x5555
+#define CONFIG_SYS_FLASH_ADDR1		0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
@@ -172,13 +172,13 @@
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
 
 #ifdef CONFIG_ENV_IS_IN_NVRAM
 #define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CONFIG_ENV_ADDR		\
-	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -186,39 +186,39 @@
  */
 
 /* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CFG_EBC_PB0AP		0x9B015480
-#define CFG_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB0AP		0x9B015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB1AP		0x02815480
-#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB1AP		0x02815480
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB2AP		0x04815A80
-#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB2AP		0x04815A80
+#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB3AP		0x01815280
-#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB3AP		0x01815280
+#define CONFIG_SYS_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
-#define CFG_EBC_PB7AP		0x01815280
-#define CFG_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_EBC_PB7AP		0x01815280
+#define CONFIG_SYS_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*-----------------------------------------------------------------------
  * External peripheral base address
  *-----------------------------------------------------------------------
  */
-#define CFG_KEY_REG_BASE_ADDR	0xF0100000
-#define CFG_IR_REG_BASE_ADDR	0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR	0xF0300000
+#define CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
+#define CONFIG_SYS_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address