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authorStefano Babic <sbabic@denx.de>2015-02-13 11:17:01 +0100
committerStefano Babic <sbabic@denx.de>2015-02-13 11:17:01 +0100
commite72d344386bf80738fab7a6bd37cb321f443093a (patch)
treed3e02055e6aa903ab80ef87c78d2f38e93981dcf /include/configs/vexpress_aemv8a.h
parent258c98f8d36ef35d7cb7604847ba73e64d702c2a (diff)
parentbd2a4888b123713adec271d6c8040ca9f609aa2f (diff)
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Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'include/configs/vexpress_aemv8a.h')
-rw-r--r--include/configs/vexpress_aemv8a.h33
1 files changed, 25 insertions, 8 deletions
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 027d78b..7fb28a5 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -11,9 +11,9 @@
/* We use generic board for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD
-#ifdef CONFIG_BASE_FVP
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
-#error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
+#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARMV8_SWITCH_TO_EL1
@@ -21,8 +21,9 @@
#define CONFIG_REMAKE_ELF
-#ifndef CONFIG_BASE_FVP
-/* Base FVP not using GICv3 yet */
+#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \
+ !defined(CONFIG_TARGET_VEXPRESS64_JUNO)
+/* Base FVP and Juno not using GICv3 yet */
#define CONFIG_GICV3
#endif
@@ -40,10 +41,13 @@
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
/* Link Definitions */
-#ifdef CONFIG_BASE_FVP
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_TEXT_BASE 0x88000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+#elif CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_TEXT_BASE 0xe0000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#else
#define CONFIG_SYS_TEXT_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
@@ -54,7 +58,7 @@
/* SMP Spin Table Definitions */
-#ifdef CONFIG_BASE_FVP
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#else
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
@@ -88,10 +92,15 @@
#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define V2M_UART0 0x7ff80000
+#define V2M_UART1 0x7ff70000
+#else /* Not Juno */
#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
+#endif
#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
@@ -119,9 +128,12 @@
#define GICR_BASE (0x2f100000)
#else
-#ifdef CONFIG_BASE_FVP
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define GICD_BASE (0x2f000000)
#define GICC_BASE (0x2c000000)
+#elif CONFIG_TARGET_VEXPRESS64_JUNO
+#define GICD_BASE (0x2C010000)
+#define GICC_BASE (0x2C02f000)
#else
#define GICD_BASE (0x2C001000)
#define GICC_BASE (0x2C002000)
@@ -140,7 +152,11 @@
/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_PL011_CLOCK 7273800
+#else
#define CONFIG_PL011_CLOCK 24000000
+#endif
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
#define CONFIG_CONS_INDEX 0
@@ -161,6 +177,7 @@
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
+#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
@@ -191,7 +208,7 @@
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Initial environment variables */
-#ifdef CONFIG_BASE_FVP
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=uImage\0" \
"kernel_addr_r=0x80000000\0" \