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authorReinhard Meyer <u-boot@emk-elektronik.de>2011-06-06 00:16:42 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-06-21 22:26:22 +0200
commit9b372b2c8e00f2e9496f68001871c287220377f9 (patch)
tree8df1c251fc3933b601b97cf9163c9240b11fceef /include/configs/top9000.h
parent8c6407fce320155a1e56645b9f95db9ac0806c26 (diff)
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AT91 rework: fix TOP9000 files to build again
Fix EMK TOP9000 board to build again: - changes required due to ATMEL rework Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Diffstat (limited to 'include/configs/top9000.h')
-rw-r--r--include/configs/top9000.h30
1 files changed, 15 insertions, 15 deletions
diff --git a/include/configs/top9000.h b/include/configs/top9000.h
index 5f0160d..5bca6e1 100644
--- a/include/configs/top9000.h
+++ b/include/configs/top9000.h
@@ -38,6 +38,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+/* SoC must be defined first, before hardware.h is included */
+#define CONFIG_AT91SAM9XE
+#include <asm/hardware.h>
+
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.
@@ -61,17 +65,11 @@
#define CONFIG_CMD_CACHE
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz xtal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
#define CONFIG_SYS_HZ 1000
-/* SoC */
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 based SoC */
-#define CONFIG_AT91SAM9XE
-
/* Misc CPU related */
-#define CONFIG_AT91_LEGACY
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
@@ -83,12 +81,14 @@
#define CONFIG_AT91RESET_EXTRST /* assert external reset */
/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */
#define CONFIG_ATMEL_USART
-#define CONFIG_USART3 /* USART 3 is DBGU !!! */
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
@@ -123,7 +123,7 @@
* with u-boot commands
*/
# define CONFIG_AT91_EFLASH
-# define CONFIG_SYS_FLASH_BASE 0x200000
+# define CONFIG_SYS_FLASH_BASE ATMEL_BASE_FLASH
# define CONFIG_SYS_MAX_FLASH_SECT 32
# define CONFIG_SYS_MAX_FLASH_BANKS 1
# define CONFIG_SYS_FLASH_PROTECTION
@@ -159,10 +159,10 @@
* Initialized before u-boot gets started.
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END 0x21e00000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01e00000)
#define CONFIG_SYS_LOAD_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x01000000)
/*
@@ -171,7 +171,7 @@
* that address while providing maximum stack area below.
*/
#define CONFIG_SYS_INIT_SP_ADDR \
- (0x00300000 + 0x4000 - GENERATED_GBL_DATA_SIZE)
+ (ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE)
/*
* NAND flash: 256 MB (optional)
@@ -184,7 +184,7 @@
*/
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
@@ -197,7 +197,7 @@
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE