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| author | Simon Glass <sjg@chromium.org> | 2015-03-03 08:03:02 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-04 14:55:04 -0500 |
| commit | 7ae8350f67eea861280a4cbd2d067777a0e87153 (patch) | |
| tree | b4e959ee796ff1e7fa172c050d67b4c0b5b71f7f /include/configs/ti_armv7_common.h | |
| parent | 905949190d4df7fc5b7c4f3e96adf219e65cad78 (diff) | |
| download | u-boot-imx-7ae8350f67eea861280a4cbd2d067777a0e87153.zip u-boot-imx-7ae8350f67eea861280a4cbd2d067777a0e87153.tar.gz u-boot-imx-7ae8350f67eea861280a4cbd2d067777a0e87153.tar.bz2 | |
ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACK
Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f(). Adjust the
code paths in these cases to be correct. In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment). In these cases switch to CONFIG_SPL_STACK_R. In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM
Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/ti_armv7_common.h')
| -rw-r--r-- | include/configs/ti_armv7_common.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 2bd1164..c0c1060 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -213,10 +213,9 @@ * SPLs). We have our BSS be placed 2MiB after this, to allow for the * default Linux kernel address of 0x80008000 to work with most sized * kernels, in the Falcon Mode case. We have the SPL malloc pool at the - * end of the BSS area. We place our stack at 32MiB after the start of - * DRAM to allow room for all of the above. + * end of the BSS area. We suggest that the stack be placed at 32MiB after + * the start of DRAM to allow room for all of the above (handled in Kconfig). */ -#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20)) #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x80800000 #endif |