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| author | Alexander Graf <agraf@suse.de> | 2016-03-04 01:09:54 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-03-15 15:13:10 -0400 |
| commit | 7985cdf74b280f86a1c7440298a84f1fb2876fd9 (patch) | |
| tree | bf567412991af90c220b90b59051d97bd5819c6d /include/configs/tegra210-common.h | |
| parent | 21845825608af7fbc5513e4fbf812426df437302 (diff) | |
| download | u-boot-imx-7985cdf74b280f86a1c7440298a84f1fb2876fd9.zip u-boot-imx-7985cdf74b280f86a1c7440298a84f1fb2876fd9.tar.gz u-boot-imx-7985cdf74b280f86a1c7440298a84f1fb2876fd9.tar.bz2 | |
arm64: Remove non-full-va map code
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.
To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'include/configs/tegra210-common.h')
| -rw-r--r-- | include/configs/tegra210-common.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 2a6e317..8f35a7b 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -13,8 +13,6 @@ /* Cortex-A57 uses a cache line size of 64 bytes */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_FULL_VA - /* * NS16550 Configuration */ |