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| author | Karlheinz Jerg <karlheinz.jerg@keymile.com> | 2013-01-21 03:55:18 +0000 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2013-02-15 17:47:20 -0600 |
| commit | 5bcd64cf5c5510365a14d11043033eb7b6144ead (patch) | |
| tree | c435d14f6deb3b6a9b25b12c4c812bf3a635dcf4 /include/configs/suvd3.h | |
| parent | 322bb2056ba90d55603f081ae57a652a06357bac (diff) | |
| download | u-boot-imx-5bcd64cf5c5510365a14d11043033eb7b6144ead.zip u-boot-imx-5bcd64cf5c5510365a14d11043033eb7b6144ead.tar.gz u-boot-imx-5bcd64cf5c5510365a14d11043033eb7b6144ead.tar.bz2 | |
powerpc/83xx/km: add MV88E6122 switch support for kmvect1
kmvect1 has a UEC2 connection to the piggy board and a UEC0 connection
to the switch MV88E6122. This switch has a connection to a frontport
ethernet interface. The ethernet port used for network booting is
automatically selected by u-boot. If a Piggy is plugged, the Piggy
port is selected (UEC2, eth1). If the Piggy isn't present, the
Frontport is selected (UEC0, eth0).
The switch reset is connected to a GPIO on the PRIO3 board FPGA (GPIO28)
and released at startup.
Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Diffstat (limited to 'include/configs/suvd3.h')
| -rw-r--r-- | include/configs/suvd3.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index c50832c..bbf9da5 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,4 +110,41 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +/* + * QE UEC ethernet configuration + */ +#if defined(CONFIG_KMVECT1) +#define CONFIG_MV88E6352_SWITCH +#define CONFIG_KM_MVEXTSW_ADDR 0x10 + +/* ethernet port connected to simple switch 88e6122 (UEC0) */ +#define CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 + +#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ +#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ + {devnum, speed, duplex} +#define CONFIG_SYS_FIXED_PHY_PORTS \ + CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) + +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 +#endif /* CONFIG_KMVECT1 */ + #endif /* __CONFIG_H */ |