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| author | Chin Liang See <clsee@altera.com> | 2014-09-19 04:28:23 -0500 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2014-10-06 17:46:51 +0200 |
| commit | ddcbed04a21857cb0a457b0ff3de26c750815632 (patch) | |
| tree | fdabeb3b37db515ca31225605582c34ac04cbb84 /include/configs/socfpga_cyclone5.h | |
| parent | 13e81d45f80b58e57a78daf6850d4f3a6bc20d9e (diff) | |
| download | u-boot-imx-ddcbed04a21857cb0a457b0ff3de26c750815632.zip u-boot-imx-ddcbed04a21857cb0a457b0ff3de26c750815632.tar.gz u-boot-imx-ddcbed04a21857cb0a457b0ff3de26c750815632.tar.bz2 | |
arm: socfpga: Enable DWMMC for SOCFPGA
Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit
Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'include/configs/socfpga_cyclone5.h')
| -rw-r--r-- | include/configs/socfpga_cyclone5.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index c8986d9..0da7059 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -251,6 +251,22 @@ /* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ 25000 +/* + * MMC support + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_SOCFPGA_DWMMC +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif /* CONFIG_MMC */ /* * SPL "Second Program Loader" aka Initial Software |