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authorMarek Vasut <marex@denx.de>2014-09-15 01:45:14 +0200
committerMarek Vasut <marex@denx.de>2014-10-06 17:46:50 +0200
commitb5e9b296251f138ef9f9cfc15f408710a24831cd (patch)
treef2ea633bcc66ea69c6c5520ded9ccd916e295838 /include/configs/socfpga_cyclone5.h
parent40e7bcdee72830fa51d9e98428f1a61f9126527e (diff)
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arm: socfpga: cache: Enable PL310 L2 cache
Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'include/configs/socfpga_cyclone5.h')
-rw-r--r--include/configs/socfpga_cyclone5.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index de60bb2..c8986d9 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -27,6 +27,8 @@
#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/* base address for .text section */
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET