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| author | Wolfgang Denk <wd@denx.de> | 2007-04-04 02:18:56 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-04-04 02:18:56 +0200 |
| commit | 25b0806fff1f1fd24f69f6d9ef04d8345667e60b (patch) | |
| tree | 38cbc11d30a3a5de01c5cfa5f5ea0da4597aad64 /include/configs/sequoia.h | |
| parent | 31c98a88228021b314c89ebb8104fb6473da4471 (diff) | |
| parent | 0e7d4916afaf83083b9b70ad779f29f7b57bd8ed (diff) | |
| download | u-boot-imx-25b0806fff1f1fd24f69f6d9ef04d8345667e60b.zip u-boot-imx-25b0806fff1f1fd24f69f6d9ef04d8345667e60b.tar.gz u-boot-imx-25b0806fff1f1fd24f69f6d9ef04d8345667e60b.tar.bz2 | |
Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx
Diffstat (limited to 'include/configs/sequoia.h')
| -rw-r--r-- | include/configs/sequoia.h | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 29f3b40..1f19621 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -33,7 +33,6 @@ *----------------------------------------------------------------------*/ /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ #ifndef CONFIG_RAINIER -#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #else #define CONFIG_440GRX 1 /* Specific PPC440GRx */ @@ -75,9 +74,7 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ - #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -381,9 +378,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_FLASH CFG_FLASH_BASE -#define CFG_NAND 0xD0000000 -#define CFG_CPLD 0xC0000000 /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting @@ -392,25 +386,25 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) #else #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017200 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 -#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) #endif /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x24814580 -#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) /*----------------------------------------------------------------------- * NAND FLASH |