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| author | Stefan Roese <sr@denx.de> | 2007-03-24 15:59:23 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-24 15:59:23 +0100 |
| commit | e50b791b3f8b696e32000bbaa6e2d1f098c4bc04 (patch) | |
| tree | 6a7953a8761f860be7f5ba8054d3582076bc10cc /include/configs/sequoia.h | |
| parent | e6615ecf4eaf4dd52696934aed8f5c6474cfd286 (diff) | |
| parent | 0d974d5297349504a2ddfa09314be573b5df320a (diff) | |
| download | u-boot-imx-e50b791b3f8b696e32000bbaa6e2d1f098c4bc04.zip u-boot-imx-e50b791b3f8b696e32000bbaa6e2d1f098c4bc04.tar.gz u-boot-imx-e50b791b3f8b696e32000bbaa6e2d1f098c4bc04.tar.bz2 | |
Merge with /home/stefan/git/u-boot/acadia
Diffstat (limited to 'include/configs/sequoia.h')
| -rw-r--r-- | include/configs/sequoia.h | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 29f3b40..8a31925 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -75,9 +75,7 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ - #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -381,9 +379,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_FLASH CFG_FLASH_BASE -#define CFG_NAND 0xD0000000 -#define CFG_CPLD 0xC0000000 /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting @@ -392,25 +387,25 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) #else #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017200 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 -#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) #endif /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x24814580 -#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) /*----------------------------------------------------------------------- * NAND FLASH |