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authorStefan Roese <sr@denx.de>2006-10-20 14:28:52 +0200
committerStefan Roese <sr@denx.de>2006-10-20 15:17:55 +0200
commit43a2b0e76a56995f17e1b7628c192ebafe6051ee (patch)
tree38eca89a07197a458f46aecc4bfc2901b54e8fc6 /include/configs/sequoia.h
parent73652699dd224dffb5cd8cca24d767bed02d7a28 (diff)
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Add board/cpu specific NAND chip select function to 440 NDFC
Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006
Diffstat (limited to 'include/configs/sequoia.h')
-rw-r--r--include/configs/sequoia.h15
1 files changed, 8 insertions, 7 deletions
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index f67fd91..3a76315 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -134,13 +134,6 @@
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
-/*-----------------------------------------------------------------------
- * NAND FLASH
- *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CFG_NAND_BASE CFG_NAND_ADDR
-
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
@@ -406,6 +399,14 @@
#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000)
/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+
+/*-----------------------------------------------------------------------
* Cache Configuration
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */