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| author | Gary Jennejohn <garyj@denx.de> | 2007-08-31 15:21:46 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-31 15:21:46 +0200 |
| commit | 81b73dec16fd1227369a191e725e10044a9d56b8 (patch) | |
| tree | 3d0fe0f95120227c7ced28cc3ff742e35d22dd71 /include/configs/sequoia.h | |
| parent | 9c02defc29b57945b600714cf61ddfd02b02fb14 (diff) | |
| download | u-boot-imx-81b73dec16fd1227369a191e725e10044a9d56b8.zip u-boot-imx-81b73dec16fd1227369a191e725e10044a9d56b8.tar.gz u-boot-imx-81b73dec16fd1227369a191e725e10044a9d56b8.tar.bz2 | |
ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.
Here the details of this patch:
o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
board-specific settings. As an example the sequoia board requires 0.
Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
CFG_PCI_CACHE_LINE_SIZE to 0.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/sequoia.h')
| -rw-r--r-- | include/configs/sequoia.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 824a812..c2e1386 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -400,7 +400,8 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ |