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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2009-09-20 20:36:04 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-24 12:05:00 -0500 |
| commit | 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab (patch) | |
| tree | 084dfd5667b06957a383a14c5a67bdbaf4b10ad6 /include/configs/sbc8548.h | |
| parent | 0c7e4d45d9fb3c9e503ee93d50572d346dae150e (diff) | |
| download | u-boot-imx-11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab.zip u-boot-imx-11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab.tar.gz u-boot-imx-11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab.tar.bz2 | |
sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/sbc8548.h')
| -rw-r--r-- | include/configs/sbc8548.h | 42 |
1 files changed, 38 insertions, 4 deletions
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 5c1411f..009931d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -197,13 +197,13 @@ #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 /* - * SDRAM on the Local Bus + * SDRAM on the Local Bus (CS3 and CS4) */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ /* - * Base Register 3 and Option Register 3 configure SDRAM. + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR3, need: @@ -221,7 +221,7 @@ #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR3, need: * 64MB mask for AM, OR3[0:7] = 1111 1100 @@ -236,6 +236,40 @@ #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 +/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |