Merge branch 'master' of /home/stefan/git/u-boot/u-boot

1 files changed, 216 insertions, 216 deletions

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index dc5a101..174149b 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -63,11 +63,11 @@
 
 #undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
-#define CFG_IMMR		0xE0000000
+#define CONFIG_SYS_IMMR		0xE0000000
 
-#undef CFG_DRAM_TEST				/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000	/* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * DDR Setup
@@ -75,7 +75,7 @@
 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
 #undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
-#define CFG_83XX_DDR_USES_CS0		/* WRS; Fsl board uses CS2/CS3 */
+#define CONFIG_SYS_83XX_DDR_USES_CS0		/* WRS; Fsl board uses CS2/CS3 */
 
 /*
  * 32-bit data path mode.
@@ -89,10 +89,10 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
-#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
 
@@ -107,72 +107,72 @@
  * Manually set up DDR parameters
  * NB: manual DDR setup untested on sbc834x
  */
-#define CFG_DDR_SIZE		256		/* MB */
-#define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
-#define CFG_DDR_TIMING_1	0x36332321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
-#define CFG_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
 
 #if defined(CONFIG_DDR_32BIT)
 /* set burst length to 8 for 32-bit data path */
-#define CFG_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
 #else
 /* the default burst length is 4 - for 64-bit data path */
-#define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
 
 /*
  * SDRAM on the Local Bus
  */
-#define CFG_LBC_SDRAM_BASE	0x10000000	/* Localbus SDRAM */
-#define CFG_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0x10000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#define CFG_FLASH_BASE		0xFF800000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* flash size in MB */
-/* #define CFG_FLASH_USE_BUFFER_WRITE */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
 				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
 				BR_V)			/* valid */
 
-#define CFG_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+#define CONFIG_SYS_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
 
-#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
 
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CFG_MID_FLASH_JUMP	0x7F000000
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000			/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
@@ -180,16 +180,16 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
-#define CFG_LBC_LBCR	0x00000000
+#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR	0x00000000
 
-#undef CFG_LB_SDRAM	/* if board has SDRAM on local bus */
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
 
-#ifdef CFG_LB_SDRAM
+#ifdef CONFIG_SYS_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -201,16 +201,16 @@
  * 0    4    8    12   16   20   24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  *
- * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CFG_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
-#define CFG_LBLAWBAR2_PRELIM	0xF0000000
-#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64M */
+#define CONFIG_SYS_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	0xF0000000
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* 64M */
 
 /*
- * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -223,65 +223,65 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  */
 
-#define CFG_OR2_PRELIM	0xFC006901
+#define CONFIG_SYS_OR2_PRELIM	0xFC006901
 
-#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
-#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 
 /*
  * LSDMR masks
  */
-#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
-#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
-				| CFG_LBC_LSDMR_BSMA1516	\
-				| CFG_LBC_LSDMR_RFCR8		\
-				| CFG_LBC_LSDMR_PRETOACT6	\
-				| CFG_LBC_LSDMR_ACTTORW3	\
-				| CFG_LBC_LSDMR_BL8		\
-				| CFG_LBC_LSDMR_WRC3		\
-				| CFG_LBC_LSDMR_CL3		\
+#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFEN            \
+				| CONFIG_SYS_LBC_LSDMR_BSMA1516	\
+				| CONFIG_SYS_LBC_LSDMR_RFCR8		\
+				| CONFIG_SYS_LBC_LSDMR_PRETOACT6	\
+				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
+				| CONFIG_SYS_LBC_LSDMR_BL8		\
+				| CONFIG_SYS_LBC_LSDMR_WRC3		\
+				| CONFIG_SYS_LBC_LSDMR_CL3		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)
-#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)
-#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)
-#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
+				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 #endif
 
 /*
@@ -289,22 +289,22 @@
  */
 #define CONFIG_CONS_INDEX     1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
-#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* pass open firmware flat tree */
@@ -317,43 +317,43 @@
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_CMD_TREE
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-#define CFG_I2C1_OFFSET		0x3000
-#define CFG_I2C2_OFFSET		0x3100
-#define CFG_I2C_OFFSET		CFG_I2C2_OFFSET
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C1_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_OFFSET		CONFIG_SYS_I2C2_OFFSET
 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
 
 /* TSEC */
-#define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CFG_PCI1_MEM_BASE	0x80000000
-#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_MMIO_BASE	0x90000000
-#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
-#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI1_IO_BASE	0x00000000
-#define CFG_PCI1_IO_PHYS	0xE2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-#define CFG_PCI2_MEM_BASE	0xA0000000
-#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_MMIO_BASE	0xB0000000
-#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
-#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xE2100000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -378,7 +378,7 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -412,9 +412,9 @@
 /*
  * Environment
  */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 
@@ -423,14 +423,14 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 
 /*
@@ -455,7 +455,7 @@
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
     #undef CONFIG_CMD_ENV
     #undef CONFIG_CMD_LOADS
 #endif
@@ -466,60 +466,60 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory */
-#define CFG_LOAD_ADDR	0x2000000	/* default load address */
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
 #if 1 /*528/264*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*396/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_3X1)
 #elif 0 /*264/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*132/132*/
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
 	HRCWL_VCO_1X4 |\
 	HRCWL_CORE_TO_CSB_1X1)
 #elif 0 /*264/264 */
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN |\
@@ -528,7 +528,7 @@
 #endif
 
 #if defined(PCI_64BIT)
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -541,7 +541,7 @@
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -556,78 +556,78 @@
 #endif
 
 /* System IO Config */
-#define CFG_SICRH SICRH_TSOBI1
-#define CFG_SICRL SICRL_LDP_A
+#define CONFIG_SYS_SICRH SICRH_TSOBI1
+#define CONFIG_SYS_SICRL SICRL_LDP_A
 
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 
-/* #define CFG_HID0_FINAL		(\
+/* #define CONFIG_SYS_HID0_FINAL		(\
 	HID0_ENABLE_INSTRUCTION_CACHE |\
 	HID0_ENABLE_M_BIT |\
 	HID0_ENABLE_ADDRESS_BROADCAST ) */
 
 
-#define CFG_HID2 HID2_HBE
+#define CONFIG_SYS_HID2 HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR @ 0x00000000 */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* PCI @ 0x80000000 */
 #ifdef CONFIG_PCI
-#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT1L	(0)
-#define CFG_IBAT1U	(0)
-#define CFG_IBAT2L	(0)
-#define CFG_IBAT2U	(0)
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
 #endif
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT3L	(0)
-#define CFG_IBAT3U	(0)
-#define CFG_IBAT4L	(0)
-#define CFG_IBAT4U	(0)
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_IBAT7L	(0)
-#define CFG_IBAT7U	(0)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions