diff options
| author | Minkyu Kang <mk7.kang@samsung.com> | 2010-11-16 09:55:11 +0900 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2010-11-16 09:55:11 +0900 |
| commit | 1032d97496f6d534bf0030a5779ff1cb38cc9ebf (patch) | |
| tree | 3713c814a7453024eceb097c67532072950e2f2e /include/configs/pxa255_idp.h | |
| parent | 37a3bda0c9c8a2ffbf7e2a9e121177a3385a0626 (diff) | |
| parent | 227b72515546fca535dbd3274f6d875d97f494fe (diff) | |
| download | u-boot-imx-1032d97496f6d534bf0030a5779ff1cb38cc9ebf.zip u-boot-imx-1032d97496f6d534bf0030a5779ff1cb38cc9ebf.tar.gz u-boot-imx-1032d97496f6d534bf0030a5779ff1cb38cc9ebf.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'include/configs/pxa255_idp.h')
| -rw-r--r-- | include/configs/pxa255_idp.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 4581674..c1c7f80 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -42,7 +42,7 @@ * so we MUST NOT initialize critical regs like mem-timing ... */ #undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ -#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */ +#define CONFIG_SYS_TEXT_BASE 0x0 /* * define the following to enable debug blinks. A debug blink function @@ -75,7 +75,6 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* * PXA250 IDP memory map information @@ -271,7 +270,7 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ @@ -293,7 +292,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) /* * GPIO settings @@ -317,6 +316,9 @@ #define CONFIG_SYS_PSSR_VAL 0x20 +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 + /* * Memory settings */ @@ -326,6 +328,8 @@ #define CONFIG_SYS_MDCNFG_VAL 0x090009C9 #define CONFIG_SYS_MDREFR_VAL 0x0085C017 #define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces |