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authorWolfgang Denk <wd@denx.de>2011-06-23 15:37:33 +0200
committerWolfgang Denk <wd@denx.de>2011-06-23 15:37:33 +0200
commit9623c158f6a5150a21c25026bfba79e7ff7912f5 (patch)
tree2c4d4209a34baa810a6f3fb409e1f8e494f01b31 /include/configs/pdnb3.h
parent2ad6e27dcdbd694de8e3823d2b52b250b1a59219 (diff)
parent1ed63c549892bc3a4ce1a43f09a6a92a00054f3d (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: run arm_pci_init after relocation IXP42x PCI rewrite update/fix PDNB3 board update/fix IXDP425 / IXDPG425 boards add dvlhost (dLAN 200 AV Wireless G) board IXP NPE: add support for fixed-speed MII ports update/fix AcTux4 board update/fix AcTux3 board update/fix AcTux2 board update/fix AcTux1 board use -ffunction-sections / --gc-sections on IXP42x support CONFIG_SYS_LDSCRIPT on ARM fix "depend" target in npe directory Fix IXP code to work after relocation was added trigger hardware watchdog in IXP42x serial driver add support for IXP42x Rev. B1 and newer add XScale sub architecture (IXP/PXA) to maintainer list Conflicts: arch/arm/lib/board.c Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs/pdnb3.h')
-rw-r--r--include/configs/pdnb3.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 33fa6ee..7fe9e5b 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -50,9 +50,6 @@
/*
* Misc configuration options
*/
-#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
-#define CONFIG_TIMER_IRQ
-
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
@@ -117,6 +114,7 @@
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
+#define CONFIG_IXP425_TIMER_CLK 66666666
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
@@ -188,6 +186,7 @@
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_FLASH_BASE 0x50000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#if defined(CONFIG_SCPU)
@@ -345,4 +344,9 @@
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */